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low power, five electrode electrocardiogram (ecg) analog front end data sheet adas1000 / adas1000 - 1 / adas1000 - 2 features biopotential s ignal s in; digitized signals out 5 acquisition (ecg) channels and one driven lead parallel ics for up to 10 + e lectrode measurements master adas1000 or adas1000 - 1 used with s lave adas1000 - 2 ac and dc lead - off detection internal pace detection algorithm on 3 leads s upport for user s own pace thoracic i mpedance meas urement (int ernal /ex t ernal path ) selectable r eference l ead scalable no ise vs. power control, powe r - down modes low power operation from 11 mw ( 1 lead), 15 mw ( 3 leads), 21 mw (all electrodes) lead or electrode data available supports aami ec11:1991/(r)2001/(r)2007, aami ec38 r2007, ec13:2002/(r)2007, iec60601 - 1 ed. 3.0 b:2005, iec60601 - 2 - 25 ed. 2.0 :20 11 , iec 60601 - 2 - 27 ed. 2.0 b: 2005 , iec 60601 - 2 - 51 ed. 1.0 b: 2005 fast overload recovery low or high speed data output rates serial interface spi - /qspi? - /dsp - compatible 56- lead lfcsp package ( 9 mm 9 mm) 64- lead lqfp package (10 mm 10 mm b ody size) applic ations ecg : monitor and d iagnostic bedside patient monitoring , portable telemetry , holter , aed, cardiac defibrillators, ambulatory monitors, pace maker programmer, pa tient transport, stress testing general description the adas1000 / adas1000 - 1 / adas1000 - 2 measure electro cardiac (ecg) signals, thoracic impedance, pacing artifacts, and lead - on/ lead - off status and output this information in the form of a data frame supplying either le ad/vector or electrode data at programmable data rates. its low power and small size make it suitable for portable, battery - powered applications. the high performance also makes it suitable for higher end diagnostic machines. the adas1000 is a full - featured , 5 - channel ecg including respiration and pace detection, while the adas1000 - 1 offers only ecg channels with no respiration or pace features. similarly, the adas1000 - 2 is a subset of the main device and is configured for gang purposes with only the ecg channels enabled (no respiration, pace , or right leg drive ). the adas1000 / adas1000 - 1 / adas1000 - 2 are designed to simplify the task of acquiring and ensuring quality ecg signals. they provide a low power, small data acquisition system for biopotential applications. auxiliary features that aid in better q uality ecg signal acquisition include multichannel averaged driven lead, selectable reference drive, fast overload recovery, flexible respiration circuitry returning magnitude and phase information, internal pace detection algorithm operating on three lea ds, and the option of ac or dc lead - off detection. several digital output options ensure flexibility when monitoring and analyzing signals. value - added cardiac post processing is executed externally on a dsp, microprocessor, or fpga. because ecg systems s pan different applications, the adas1000 / adas1000 - 1 / adas1000 - 2 feature a power/ noise scaling architecture where the noise can be reduced at the expense of increasing power cons umption. signal acquisition channels can be shut down to save power. data rates can be reduced to save power. to ease manufacturing tests and development as well as offer holistic power - up testing, the adas1000 / adas1000 - 1 / adas1000 - 2 offer a suite of feature s, such as dc and ac test excitation via the calibration dac and cyclic redundancy check (crc) redundancy testing , in addition to readback of all relevant register address s pace. the input structure is a differential amplifier input , thereby allowing users a variety of configuration options to best suit their application. the adas1000 / adas1000 - 1 / a das1000 - 2 are available in two package options , a 56 - lead lfcsp package and a 64 - lead lqfp package . both packages are specified over a ? 40 c to + 85 c temperature range. rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog device s for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analo g devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2014 analog devices, inc. all rights r eserved. technical support www.analog.com
adas1000/adas1000 - 1/adas1000 - 2 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 noise performance ....................................................................... 9 timing characteristics .............................................................. 10 absolute maximum ratings .......................................................... 13 thermal resistance .................................................................... 13 esd caution ................................................................................ 13 pin configurations and function descriptions ......................... 14 typical performance characteristics ........................................... 18 applications information .............................................................. 25 overview ...................................................................................... 25 ecg inputs electrodes/leads ................................................ 28 ecg channel .............................................................................. 29 electrode/lead formation and input stage configuration .. 30 defibrillator protection ............................................................. 34 e sis filtering ............................................................................... 34 ecg path input multiplexing ................................................... 34 common - mode selection and averaging .............................. 35 wilson central terminal (wct) ............................................. 36 right leg drive/reference drive ............................................. 36 calibration dac ......................................................................... 37 gain calibration ......................................................................... 37 lead - off detection .................................................................... 37 shield driver ............................................................................... 38 respiration (adas1000 model only) ..................................... 38 evaluating respiration performance ....................................... 41 extend switch on respir ation paths ....................................... 41 pacing artifact detection function (adas1000 only) ....... 42 biventricular pacers ................................................................... 45 pace detection measurements ................................................. 45 evaluating pace detection performance ................................. 45 pace width .................................................................................. 45 pace latency ................................................................................ 45 pace detection via secondary serial interface (adas1000 and adas1000 - 1 only) ............................................................ 45 filtering ....................................................................................... 46 voltage reference ....................................................................... 47 gang mode operation ............................................................... 47 interfacing in gang mode ......................................................... 49 serial interfaces ............................................................................... 50 standard serial interface ........................................................... 50 secondary serial interface ......................................................... 54 reset .......................................................................................... 54 pd function ................................................................................ 54 spi output frame structure (ecg and status data) ................ 55 spi register definitions and memory map ................................ 56 control registers details ............................................................... 57 examples of interfacing to the adas1000 ............................. 74 software flowchart .................................................................... 77 power supply, grounding, and decoupling strategy ............ 78 avdd .......................................................................................... 78 adcvdd and dvdd supplies ............................................... 78 unused pins/paths ..................................................................... 78 layout recommendations ........................................................ 78 outline dimensions ....................................................................... 79 ordering guide .......................................................................... 80 rev. b | page 2 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 revision history 6/ 14 rev. a to rev. b moved revision history ................................................................... 3 change to ac lead - off , frequency range parameter, table 2 .. 7 changes to figure 17 ...................................................................... 1 8 ch anges to figure 40 and figure 41 ............................................. 2 2 changes to ecg channel section ................................................ 29 replaced figure 57 .......................................................................... 30 added figure 58, figure 59, figure 60, figure 61 , and figure 62 ; renumbered sequentially .............................................................. 3 1 deleted figure 6 3 , figure 64, and figure 65; renumbered sequentially ...................................................................................... 3 5 change to figure 6 5 , figure 6 6 , and figure 6 7 ........................... 3 5 changes to lead - off detection section , added figure 68; renumbered sequentially .............................................................. 3 7 changes to respiration (adas1000 model only) section and figure 69 , figure 7 0 , and figure 7 1 ; added table 13 and table 14; r enumbered sequentially .............................................. 39 changes to pacing artifact detection function (adas1000 only) section ................................................................................... 4 2 changes to evaluating pace detection performance section ... 4 5 added pace width section ............................................................ 4 5 changes to standard serial interface section .............................. 5 0 changes to data ready ( drd ) section ..................................... 5 2 changes to secondary serial interface section and table 25 .... 5 4 change to bit 3, table 28 ................................................................ 5 7 changes to table 43 ........................................................................ 6 7 change to table 45 .......................................................................... 68 changes to table 50 ........................................................................ 7 0 changes to table 52 ........................................................................ 7 1 changes to table 53 ........................................................................ 7 2 1/1 3 rev. 0 t o rev. a changes to features section ............................................................ 1 changes to table 1 ............................................................................ 3 changes to excitation current, test conditions/comments, table 2 ................................................................................................. 5 added table 3 ; renumbered sequentially ..................................... 9 changes to respiration (adas1000 model only) section, figure 66, and internal respiratio n capacitors section ............ 37 changes to figure 67 ...................................................................... 38 changes to figure 68 ...................................................................... 39 added evaluating pace detection performance section ........... 43 added table 15 ................................................................................ 47 changes to clocks section ............................................................. 51 changes to respamp name, function, table 2 8 ...................... 5 7 changes to bits14:9, function, ta ble 30 ................................... 59 changes to ordering guide ........................................................... 78 8/ 12 revision 0 : initial version rev. b | page 3 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet functional block dia gram figure 1 . adas1000 full featured mod el table 1 . overview of features available from adas1000 generics generic 1 ecg operation right leg drive respiration pace detection shield driver master interface 2 package option adas1000 5 ecg channels master/slave yes yes yes yes yes lfcsp, lqfp adas1000 - 1 5 ecg channels master/slave yes yes yes lfcsp adas1000 - 2 5 ecg channels slave lfcsp, lqfp adas1000 - 3 3 ecg channels master/slave yes yes yes lfcsp, lqfp adas1000 - 4 3 ecg channels master/slave yes yes yes yes yes lfcsp, lqfp 1 the adas1000 - 2 is a companion device for increased channel count purposes . it has a subset of features and is not intended for standalone use . it can be used in conjunction wit h any master device. 2 master interface is provided for users wishing to utilize their own digital pace algorithm; see the secondary serial interface section. electrodes 5 vref refout refin cal_dac_io amp adc respiration path muxes ac lead-off dac calibration dac amp adc 5 ecg path filters, control, and interface logic pace detection cs sclk sdi sdo drdy gpio3 gpio1/msclk gpio2/msdo gpio0/mcs ac lead-off detection ? + common- mode amp rld_sj driven lead amp shield drive amp shield rld_out cm_in xtal1 xtal2 iovdd clock gen/osc/ external clk source ext_resp_la ext_resp_ll vcm_ref (1.3v) clk_io avdd adcvdd dvdd ext_resp_ra cm_out/wct 10k? adcvdd, dvdd 1.8v regulators adas1000 buffer respiration dac 09660-001 rev. b | page 4 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 specifications avdd = 3.3 v 5 % , iovdd = 1. 65 v to 3. 6 v, agnd = dgnd = 0 v, refin tied to refout, externally supplied crystal/clo ck = 8.192 mhz. decoupling for reference and supplies as noted in the power supply, grounding, and decoupling strategy section . t a = ? 40c to + 85c , unless otherwise noted. typical specifications are mean values at t a = 25c . for specified performance, internal adcvdd and dvdd linear regulators have been used. they may be supplied from external regulators. adcvdd = 1.8 v 5%, dvdd = 1 .8 v 5 %. front - end gain settings: gain 0 = 1.4 , gain 1 = 2.1 , gain 2 = 2.8 , gain 3 = 4.2 . table 2. parameter min typ max unit test conditions/ comments ecg channel these s pec ifications apply to the following pins: ecg1_ l a, ecg2_ ll, ecg3_ ra, ecg4_ v1, ecg5_ v2, cm_in (ce mode), ext_resp_ xx pins when used in extend switch mode electrode input range independent of supply 0.3 1.3 2.3 v gain 0 ( gain setting 1.4) 0.63 1.3 1.97 v gain 1 ( gain setting 2.1) 0.8 1.3 1.8 v gain 2 ( gain setting 2.8) 0.97 1.3 1.63 v gain 3 ( gain setting 4.2) input bias current ? 40 1 + 40 na relates to each electr ode input ; o ver operating range; dc and ac lead - off are disabled ? 200 + 200 na agnd to avdd input offset ? 7 mv electrode / v ector mode with vcm = vcm_ref gain 3 ? 7 mv gain 2 ? 15 mv gain 1 ? 22 mv gain 0 input offset tempco 1 2 v/c input amplifier input impedance 2 1 ||10 g ||pf at 10 hz cmrr 2 105 110 db 51 k imbalance, 60 hz with 300 mv differential dc offset; per aami/iec standards ; w ith driven leg loop closed crosstalk 1 80 db between channels resolution 2 19 bits electrod e/vector mode, 2 khz data rate, 24 - bit data - word 18 bits electrode/vector mode, 16 khz data rate, 24 - bit data - word 16 bits electrode / analog lead mode, 128 khz data rate, 16 - bit data - word integral nonlinearity error 30 ppm gain 0; all data rate s differential nonlinearity error 5 ppm gain 0 gain 2 referred to input. (2 vref)/gain/(2 n ? 1); a pplies after factory calibration; u ser cali bration adjust s this number gain 0 ( 1.4) 4.9 v/lsb at 19 - bit level in 2 khz data rate 9.81 v/lsb at 18 - bit level in 16 khz data rate 39.24 v/lsb at 16 - bit level in 128 khz data rate gain 1 ( 2.1) 3.27 v/lsb at 19 - bit level in 2 khz data rate 6.54 v/lsb at 18 - bit level in 16 khz data rate 26.15 v/lsb at 16 - bit level in 128 khz data rate gain 2 ( 2.8) 2.45 v/lsb at 19 - bit level in 2 khz data rate 4.9 v/lsb at 18 - bit level in 16 khz data rate 19.62 v/lsb at 16 - bit level in 128 khz data rate gain 3 ( 4.2) 1.63 v/lsb no factory calibration for this gain setting at 19 - bit level in 2 khz data rate 3.27 v/lsb at 18 - bit level in 16 khz data rate 13.08 v/lsb at 16 - bit level in 128 khz data rate gain error ? 1 + 0.01 + 1 % gain 0 to gain 2, factory calibrated ; p rogrammable user or facto ry calibration option enables; f a ctory gain calibration applies only to standard ecg interface ? 2 + 0.1 + 2 % gain 3 setting , no fa ctory calibration for this gain rev. b | page 5 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet parameter min typ max unit test conditions/ comments gain matching ? 0.1 + 0.02 + 0.1 % gain 0 to gain 2 ? 0.5 + 0.1 + 0.5 % gain 3 gain tempco 1 25 ppm/c input referred noise 1 gain 2, 2 khz data rate , see table 4 analog lead mode 6 v p - p 0.5 hz to 40 hz; h igh performance mode 10 v p - p 0.05 hz to 150 hz ; h igh performance mode 12 v p - p 0.05 hz to 150 hz; l ow power mode electrode mode 11 v p - p 0.05 hz to 150 hz; h igh performance mode 12 v p - p 0.05 hz to 150 hz; l ow power mode digital lead mode 14 v p - p 0.05 hz to 150 hz; h igh performance mode 16 v p - p 0.05 hz to 150 hz; l ow power mode power supply sensi tivity 2 100 db at 120 hz analog channel bandwidth 1 65 khz dynamic range 1 104 db gain 0, 2 khz data r ate , ?0.5 dbfs input signal, 10 hz signal - to- noise ratio 1 100 db ? 0.5 db fs input signal common - mode in put cm_in pin input voltage range 0.3 2.3 v input impedance 2 1||10 g||pf input bias current ? 40 1 + 40 na over operating range; dc and ac lead - off disabled ? 200 + 200 na agnd to avdd common - mode out put cm_out pin vcm_ref 1.28 1.3 1.32 v internal voltage; independent of supply output volt age, vcm 0.3 1.3 2.3 v no dc load output impedance 1 0.75 k not intended to drive current short circuit current 1 4 ma electrode summation weighting er ror 2 1 % resistor matching error respiration function ( adas1000 only ) these s pec ification s apply to the following pins: ex t _ r esp_la, ext_resp_ll, ext_resp_ra and selected internal respiration path s (lead i, lead ii, lead iii) input voltage range 0.3 2.3 v ac - coupled, independent of supply input voltage range (linear operation) 1.8/gain v p - p programmable gain (10 states ) input bias current ? 10 1 + 10 na applies to ext_resp_xx pins over agnd to avdd input referred noise 1 0.85 v rms frequency 2 46.5 to 64 khz programma ble frequency , see table 30 excitation current respiration drive current corresponding to differential voltage programmed by respamp bits in respctl register. internal respiration mode, cable 5 k/200 pf, 1.2 k chest impedance 64 a p - p drive range a 32 a p - p drive range b 2 16 a p - p drive range c 2 8 a p - p drive range d 2 resolution 2 24 bits update rate 125 hz measurement resolution 1 0.2 cable <5 k/200 pf per electrode, body resistance modeled as 1.2 k 0. 0 2 no cable impedance, b ody resistance modeled as 1.2 k in - amp gain 1 1 to 10 digitally programmable in steps of 1 gain error 1 % lsb weight for gain 0 setting gain tempco 1 25 ppm/c right leg drive/driven lead ( adas1000 / adas1000 - 1 only ) output voltage range 0.2 avdd ? 0.2 v rld_out short circuit current ? 5 2 + 5 ma external protection resistor required to meet regulatory patient current limits; output shorted to avdd/agnd closed - loop gain range 2 25 v/v slew rate 2 200 mv/ms input referred noise 1 8 v p - p 0.05 hz to 150 hz amplifier gbp 2 1.5 mhz rev. b | page 6 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 parameter min typ max unit test conditions/ comments dc lead - of f internal current source , pulls up open ecg pins ; p rogrammable in 10 na steps: 10 na to 70 na lead - off current accuracy 10 % of programmed value high threshold level 1 2.4 v inputs are compared to threshold levels; if inputs exceed levels, lead - off flag is raised low threshold level 1 0.2 v threshold accuracy 25 mv ac lead - off programmable in 4 steps: 12.5 na rms, 25 na rms, 50 na rms, 100 na rms frequency range 2. 039 khz fixed frequency lead - off current accuracy 10 % of programmed value, measured into low impedance refin input range 2 1.76 1.8 1.84 v channel gain scales dire ctly with refin input current 113 a per active adc 450 675 950 a 5 ecg channels and respiration enabled refout on - chip reference voltage for adc; not intended to drive other components reference inputs directly, must be buffered externally output voltage , vref 1.7 85 1.8 1. 815 v reference tempco 1 10 ppm/c output impedance 2 0.1 short circuit current 1 4.5 ma short circuit to ground voltage noise 1 33 v p - p 0.05 hz to 150 hz (ecg band) 17 v p - p 0.05 hz to 5 hz ( r espiration) calibration dac available on cal_dac_i o (output for master, input for slave) dac resoluti on 10 bits full - scale output voltage 2. 64 2.7 2. 76 v no load, nominal fs output is 1.5 refout zero - scale output voltage 0.24 0.3 0.36 v no load dnl ? 1 +1 lsb output series resistance 2 10 k not intended to drive low impedance load, used for slave cal_dac_io configured as an input input current 5 na when used as input calibration dac test tone output voltage 0.9 1 1.1 mv p - p rides on common - mode voltage, vcm_ref = 1.3 v square wave 1 hz low frequency sine wave 10 hz high frequency sine wave 150 hz shield driver ( adas1000 / adas1000 - 1 only ) output voltage range 0.3 2.3 v rides on common - mode voltage, vcm gain 1 v/v offset voltage ? 20 +20 mv short circuit current 15 25 a output current limited by internal se ries resistance stable capacitive load 2 10 nf crystal oscillator applied to xtal1 and xtal2 frequency 2 8.192 mhz start - up time 2 15 ms internal startup clock_io external c lock source supplied to clk_io ; t his pin is configured as an input when the device is programmed as a slave operating frequency 2 8.192 mhz input duty cycle 2 20 80 % output duty cycle 2 50 % digital inputs applies to all digital inputs input low voltage, v il 0.3 iovdd v input high voltage, v ih 0.7 iovdd v input current, i ih , i il ? 1 +1 a ? 20 +20 a reset has an internal pull - up pin capacitance 2 3 pf rev. b | page 7 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet parameter min typ max unit test conditions/ comments digital outputs output low voltage, v ol 0.4 v i sink = 1 ma output high voltage, v oh iovdd ? 0.4 v i source = ?1 ma output rise/fall time 4 ns capacitive load = 15 pf, 20% to 80% dvdd regulator internal 1.8 v regulator for dvdd output voltage 1.75 1.8 1.85 v available current 1 1 ma droop < 1 0 mv ; for external device loading purposes short circuit current limit 40 ma adcvdd regulator internal 1.8 v regulator for adcvdd; not recommended as a supply for other circuitry output voltage 1.75 1.8 1.85 v short circuit current limit 40 ma power supply ranges 2 avdd 3.15 3.3 5.5 v iovdd 1.65 3.6 v adcvdd 1.71 1.8 1.89 v if applied by external 1.8 v regulator dvdd 1.71 1.8 1.89 v if applied by external 1.8 v regulator power suppl y currents avdd standby current 785 975 a iovdd standby current 1 60 a externally supplied adcvdd and dvdd all 5 channels enabled, rld enabled, p ace enabled avdd current 3.4 6.25 ma high performance mode 3.1 5.3 ma low performance mo de 4.25 6.3 ma high performance mode, r espiration enabled adcvdd current 6 .2 9 ma high performance mode 4.7 6.5 ma low performance mode 7 9 ma high performance mode , r espiration enabled dvdd current 2.7 5 ma high performance mode 1.4 3.5 ma low performance mode 3.4 5.5 ma high performance mode , r espiration enabled internally supplied adcvdd and dvdd all 5 channels enabled, rld enabled, p ace enabled avdd current 1 2 .5 15.3 ma high performance mode 9 .4 12.4 ma low performance mode 14.8 17.3 ma high performance mode, r espiration enabled power dissipation all 5 channels enabled, rld enabled, p ace enabled externally supplied adcvdd and dvdd 3 all 5 input channels and rld 27 mw high performance (low noise) 21 mw low power mode internally supplied adcvdd and dvdd all 5 channels enabled, rld enabled, p ace enabled all 5 input channels and rld 41 mw high performance (low noise) 31 mw low power mode other functions 4 power dissipation respiration 7 . 6 mw shield driver 150 w 1 guaranteed by characterization, not production tested. 2 guaranteed by design, not production tested. 3 adcvdd and dvdd can be powered from an internal ldo or , alternatively , can be powered from external 1.8 v rail , which may result in a lower power solution. 4 pace is a digital function and incurs no power penalty. rev. b | page 8 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 noise performance table 3 . typical input referred noise over 0.5 second window ( v p - p) 1 mode data rate 2 gain 0 ( 1.4 ) 1 vcm gain 1 ( 2.1 ) 0.67 vcm gain 2 ( 2.8 ) 0.5 vcm gain 3 ( 4.2 ) 0.3 vcm analog lead mode 3 high performance mode 2 khz ( 0.5 hz to 40 hz) 8 6 5 4 2 khz ( 0.05 hz to 150 hz) 14 11 9 7.5 1 typ ical values measured at 25c , not subject to production test. 2 data gathered using the 2 khz packet/frame rate is measured over 0.5 seconds. the adas1000 internal programmable l ow - pass filter is configured for either 40 hz or 150 hz bandwidth. the data is gathered and post processed using a digital filter of either 0.05 hz or 0.5 hz to provide data over noted frequency bands. 3 analog lead mode as shown in figure 58. table 4. typical input referred noise (v p - p ) 1 mode data rate 2 gain 0 ( 1.4) 1 vcm gain 1 ( 2.1) 0.67 vcm g ain 2 ( 2.8) 0.5 v cm gain 3 ( 4.2) 0.3 v cm analog lead mode 3 high performance mode 2 khz ( 0.5 hz to 40 hz) 12 8.5 6 5 2 khz ( 0.05 hz to 150 hz) 20 14.5 10 8.5 2 khz (0.05 hz to 250 hz) 27 18 14.5 10.5 2 khz (0.05 hz to 450 hz) 33.5 24 19 13.5 16 khz 95 65 50 39 128 khz 180 130 105 80 low power mode 2 khz ( 0.5 hz to 40 hz) 13 9.5 7.5 5.5 2 khz ( 0.05 hz to 150 hz) 22 15.5 12 9 16 khz 110 75 59 45 128 khz 215 145 116 85 electrode mode 4 high performance mode 2 khz (0.5 hz to 40 hz) 13 9.5 8 5.5 2 khz ( 0.05 hz to 150 hz) 21 15 11 9 2 khz (0.05 hz to 250 hz) 26 19 15.5 11.5 2 khz (0.05 hz to 450 hz) 34.5 25 20.5 14.5 16 khz 100 70 57 41 128 khz 190 139 110 85 low power mode 2 khz ( 0.5 hz to 40 hz) 14 9.5 7.5 5.5 2 khz ( 0.05 hz to 150 hz) 22 15.5 12 9.5 16 khz 110 75 60 45 128 khz 218 145 120 88 digital lead mode 5 , 6 high performance mode 2 khz ( 0.5 hz to 40 hz) 16 11 9 6.5 2 khz ( 0.05 hz to 150 hz) 25 19 15 10 2 khz (0.05 hz to 250 hz) 34 23 18 13 2 khz (0.05 hz to 450 hz) 46 31 24 17.5 16 khz 130 90 70 50 low power mode 2 khz ( 0.5 hz to 40 hz) 18 12.5 10 7 2 khz ( 0.05 hz to 150 hz) 30 21 16 11 16 khz 145 100 80 58 1 typical values measured at 25c , not subject to production test. 2 data gathered using the 2 khz packet/frame rate is measured over 20 seconds. the adas1000 internal programmable low - pass filter is configured for either 40 hz or 150 hz bandwidth. the data is gathered and post processed using a digital filter of either 0.05 hz or 0.5 hz to provide data over noted frequency bands. 3 analog lead mode a s shown in figure 58. 4 single - ended input electrode mode as shown in figure 61 . electrode mode refers to common electrode a, common electrode b, and single - ended input ele ctrode configurations. see electrode/lead formation and input stage configuration section. 5 digital lead mode as shown in figure 59. 6 digital lead mode is available in 2 khz and 16 khz data rates. rev. b | page 9 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet timing characteristi cs standard serial interface avdd 33 v 5 iovdd 165 v to 36 v agd dgd 0 v refi tied to refot externally supplied crystal/clock 12 mhz t a 40c to 5c unless otherwise noted typical specifications are mean values at t a 25c table 5 iovdd parameter 1 3.3 v 2.5 v 1.8 v unit description output rate 2 2 128 khz acro ss specified iovdd supply range; t hree pro grammable output data rates available a s configured in frmctl register ( see table 37) 2 khz, 16 khz, 128 khz; use skip mode for slower rates sclk cycle time 25 40 50 ns min see table 21 for detail s on sclk vs. packet data rates t cssa 8.5 9.5 12 ns min cs valid setup time to rising sclk t csha 3 3 3 ns min cs valid hold time to rising sclk t ch 8 8 8 ns min sclk high time t cl 8 8 8 ns min sclk low time t do 8.5 11.5 20 ns typ sclk falling edge to sdo valid delay; sdo capacitance of 15 pf 11 19 24 ns max t ds 2 2 2 ns min sdi valid setup time from sclk rising edge t dh 2 2 2 ns min sdi valid hold time from sclk rising edge t cssd 2 2 2 ns min cs valid setup time from sclk rising edge t cshd 2 2 2 ns min cs valid hold time from sclk rising edge t csw 25 40 50 ns min cs high time between writes (if used). note that cs is an optional input, it may be tied permanently low. see a full description in the serial interfaces section. t drdy_cs 2 0 0 0 ns min drdy to cs s etup time t cso 6 7 9 ns typ delay from cs assert to sdo active reset low time 2 20 20 20 ns min minimum pulse width ; reset is edge triggered 1 guaranteed by characterization, not production tested. 2 guaranteed by design, not production tested. figure 2 . data read and write timing diagram (cpha = 1, cpol = 1) db[30] db[31] db[0] db[1] db[29] db[25] db[24] db[23] sclk cs sdi t ch t cl t cssa t csha t cshd t cssd t dh t ds t csw sdo t do r/w msb lsb data address do_25 last do_1 last do_0 last do_29 last do_30 last do_31 last drdv msb lsb 096 60-0 02 t cso rev. b | page 10 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 3 . starting read frame data (cpha = 1, cpol = 1) figure 4 . data read and write timing diagram (cpha = 0, cpol = 0) sc l k cs sd i t ch t cssa t csha t cshd t cssd t dh t ds sd o t do db[3 0] n db[3 1] n r/w d b [ 0 ] n db[2 9] n db[2 5] n msb lsb db[2 4] n data msb lsb drdy t cso drd y t drdy_cs db[30] n + 1 db[31] n + 1 db[0] n + 1 msb lsb db[1] n + 1 data = nop or 0x40 msb db[3 1] n db[0] n db[3 0] n db[1 ] n lsb d b[ 30] n ? 1 d b[ 31] n ? 1 d b[ 1] n ? 1 d b[ 0] n ? 1 d b[ 23] n ? 1 d b[ 25] n ? 1 previo us data header (first word of frame) db[1 ] db[23] t cl t csw address = 0x40 (fram es) 096 60-0 03 d b[ 24] n ? 1 s c l k c s s d i t c h t c l t c s h a t c s h d t c s s d t d h t d s t c s w s d o d o _ 2 8 l a s t d o _ 2 9 l a s t d o _ 3 0 l a s t d o _ 1 l a s t d o _ 0 l a s t d b [ 3 0 ] d b [ 2 9 ] d b [ 2 8 ] d b [ 2 4 ] d b [ 1 ] d b [ 0 ] l s b m s b m s b l s b t d o t d o d a t a a d d r e s s r / w d o _ 3 1 l a s t t c s s a d b [ 3 1 ] 0 9 6 6 0 - 0 0 4 d b [ 2 ] rev. b | page 11 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet secondary serial interface (master interface for customer - based digital pace algorithm ) adas1000 / adas1000 - 1 only avdd = 3.3 v 5%, iovdd = 1.65 v to 3.6 v, agnd = dgnd = 0 v, refin tied to refout, externally supplied crystal/clock = 8.192 mhz. t a = ? 40c to + 85c , unless otherwise noted. typical specifications are mean values at t a = 25c. the following timing specifications apply for the master interface when ecgctl register is configured for h igh p erformance mode (ecgctl[3] = 1) , see table 28. table 6. parameter 1 min typ max unit description output frame rate 2 128 khz all five 16 - bit ecg data - words are available at frame rate of 128 khz only f sclk 2 2.5 crystal frequency mh z crystal f requency = 8.192 mhz t mc ssa 24.4 ns m cs valid setup time t mdo 0 ns msclk rising edge to msdo valid delay t m cshd 48.8 ns mcs valid hold time from m sclk falling edge t mcsw 2173 ns mcs high time , spifw = 0, mcs asserted for entire frame as shown in figure 5, and configured in table 33 2026 ns mcs high time, spifw = 1, mcs asserted for each word in frame as shown in figure 6 and configured in table 33 1 guaranteed by characterization, not production tested. 2 guaranteed by design, not production tested. figure 5 . data read and write timi ng diagram for spifw = 0, showing entire packet of data ( header , 5 ecg words, and crc word ) figure 6 . data read and write timing diagram for spifw = 1, showing entire packet of data (header, 5 ecg words, and crc word) t msclk t mcssa 09660-105 t msclk 2 msclk mcs t mcshd msdo d0_15 t mdo msb d0_14 d0_1 d1_15 lsb spifw = 0* d5_0 d0_0 d1_14 *spifw = 0 provides mcs for each frame, sclk stays high for 1/2 msclk cycle between each word. d6_15 msb d6_14 msb lsb d6_0 lsb header: 0xf and 12-bit counter 5 16-bit ecg data 16-bit crc word t mcsw t msclk t mcssa t mcshd msclk mcs msdo spifw = 1* t msclk t mcsw d 0 _ 1 5 t mdo m s b d 0 _ 1 4 d 0 _ 1 d 1 _ 1 5 l s b d 5 _ 0 d 0 _ 0 d 1 _ 1 4 d 6 _ 1 5 m s b d 6 _ 1 4 m s b l s b d 6 _ 0 l s b 5 16-bit ecg data header: 0xf and 12-bit counter 16-bit crc word 09660-005 *spifw = 1 provides mcs for each frame, sclk stays high for 1 msclk cycle between each word. rev. b | page 12 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 absolute maximum ratings table 7. parameter rating avdd to agnd ? 0.3 v to + 6 v iovdd to dgnd ? 0.3 v to + 6 v adcvdd to agnd ? 0.3 v to + 2.5 v dvdd to dgnd ? 0.3 v to + 2.5 v refin/refout to refgnd ? 0.3 v to + 2.1 v ecg and analog inputs to agnd ? 0.3 v to avdd + 0.3 v digital inputs to dgnd ? 0.3 v to iovdd + 0.3 v refin to adcvdd adcvdd + 0.3 v agnd to dgnd ? 0.3 v to + 0.3 v refgnd to agnd ? 0.3 v to + 0.3 v ecg input continuous current 10 ma storage temperature range ? 65c to +12 5 c operating junction temperature range ? 40 c to +85 c reflow profile j - std 20 (jedec) junction temperature 150 c max esd hbm 2500 v ficdm 1000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. thermal resistance ? ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 8 . thermal resistance 1 package type ja unit 56- lead lfcsp 35 c/w 64- lead lqfp 42.5 c/w 1 based on jedec standard 4 - layer (2s2p) high effective thermal conductivity test board (jesd51 - 7) and natural convection. esd caution rev. b | page 13 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet pin configuration s and function descrip tions figure 7 . adas1000 64 - lead lqfp pin configuration figure 8 . adas1000 56 - lead lfcsp pin configuration figure 9 . adas1000 - 1 56 - lead lfcsp pin configuration dgnd iovdd gpio0/mcs gpio1/msclk gpio2/msdo gpio3 dgnd cs drdy sdi sclk sdo iovdd dgnd nc nc dgnd dvdd sync_gang pd reset adcvdd agnd agnd avdd vreg_en shield/respdac_la cal_dac_io respdac_ll avdd nc nc p i n 1 ad as1000 64-lead lqfp top view (not to scale) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 ext_resp_la ext_resp_ll refgnd refout refin ecg1_la ecg2_ll ext_resp_ra agnd ecg4_v1 respdac_ra agnd nc ecg5_v2 nc ecg3_ra cm_out/wct rld_sj avdd agnd agnd adcvdd xtal1 rld_out dgnd clk_io cm_in avdd nc dvdd nc xtal2 notes 1. nc = no connect. do not connect to this pin. 09660-007 pin 1 indicator 1 agnd 2 respdac_ra 3 ext_resp_ra 4 ext_resp_ll 5 ext_resp_la 6 refgnd 7 refout 8 refin 9 ecg1_la 10 ecg2_ll 11 ecg3_ra 12 ecg4_v1 13 ecg5_v2 14 agnd 35 dgnd 36 cs 37 drdy 38 sdi 39 sclk 40 sdo 41 iovdd 42 dgnd notes 1. the exposed paddle is on the top of the package; it is connected to the most negative potential, agnd. 34 gpio3 33 gpio2/msdo 32 gpio1/msclk 31 gpio0/mcs 30 iovdd 29 dgnd 15 avdd 16 cm_in 17 rld_out 19 cm_out/wct 21 agnd 20 avdd 22 agnd 23 adcvdd 24 xtal1 25 xtal2 26 clk_io 27 dvdd 28 dgnd 18 rld_sj 45 sync_gang 46 pd 47 reset 48 adcvdd 49 agnd 50 agnd 51 avdd 52 vreg_en 53 shield/respdac_la 54 cal_dac_io 44 dvdd 43 dgnd adas1000 56-lead lfcsp top view (not to scale) 55 respdac_ll 56 avdd 09660-006 pin 1 indicator 1 agnd 2 nc 3 nc 4 nc 5 nc 6 refgnd 7 refout 8 refin 9 ecg1_la 10 ecg2_ll 11 ecg3_ra 12 ecg4_v1 13 ecg5_v2 14 agnd 35 36 37 38 39 40 41 42 34 33 32 31 30 29 15 avdd 16 cm_in 17 rld_out 19 cm_out/wct 21 agnd 20 avdd 22 agnd 23 adcvdd 24 xtal1 25 xtal2 26 clk_io 27 dvdd 28 dgnd 18 rld_sj 45 sync_gang 46 pd 47 reset 48 adcvdd 49 agnd 50 agnd 51 avdd 52 vreg_en 53 shield 54 cal_dac_io 44 dvdd 43 dgnd adas1000-1 56-lead lfcsp top view (not to scale) 55 nc 56 avdd dgnd cs drdy sdi sclk sdo iovdd dgnd gpio3 gpio2/msdo gpio1/msclk gpio0/mcs iovdd dgnd 09660-008 notes 1. the exposed paddle is on the top of the package; it is connected to the most negative potential, agnd. rev. b | page 14 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 10 . adas1000 - 2 companion 64 - lead lqfp pin configuration figure 11 . adas1000 - 2 companion 56 - lead lfcsp pin configuration table 9 . pin function descriptions adas1000 adas1000 - 1 adas1000 - 2 mnemonic description lfp lfcsp lfcsp lfp lfcsp 18, 23, 58, 63 15, 20, 51, 56 15, 20, 51, 56 18, 23 , 58, 63 15, 20, 51, 56 avdd analog supply . see recommendations for bypass capacitors in the power supply, grounding, and decoupling strategy section. 35, 46 30, 41 30, 41 35, 46 30, 41 iovdd digital supply for d igital input/output voltage levels. see recommendations for bypass capacitors in the power supply, grounding, and decoupling strategy section. 26, 55 23, 48 23, 48 26, 55 23, 48 adcvdd analog supply for adc. t here is an on - chip linear regulator providing the supply voltage for the adcs . t his pin is primarily provided for decoupling purposes ; however, the pin may also be supplied by an external 1.8 v supply if the user wants to use a more efficient supply to min imize power dissipation. in this case, use the vreg_en pin tied to ground to disable the adcvdd and dvdd regulators. do not use t he adcvdd to supply other functions. see recommendations for bypass capacitors in the power supply, grounding, and decoupling strategy section. 30, 51 27, 44 27, 44 30, 51 27, 44 dvdd digital supply. there is an on - chip linear regulator providing the supp ly voltage for the digital core. t his pin is primarily provided for decoupling purpo ses ; however, the pin can also be overdriven , supplied by an external 1.8 v supply if the user w ants to use a more efficient supply to minimize power dissipation. in this case, use the vreg_en pin tied to ground to disable the adcvdd and dvdd regulators. s ee recommendations for bypass capacitors in the power supply, grounding, and decoupling strategy section. 2, 15, 24, 25, 56, 57 1, 14, 21, 22, 49, 50 1, 14, 21, 22, 49, 50 2, 15, 24, 25, 56, 57 1, 14, 21, 22, 49, 50 agnd analog ground . 31, 34, 40, 47, 50 28, 29, 36, 42, 43 28, 29, 36, 42, 43 31, 34, 40, 47, 50 28, 29, 36, 42, 43 dgnd digital ground . 59 19 19 59 19 vreg_en enables or disables the internal voltage regulators used for adcvdd and dvdd. tie this pin to avdd to enable or tie this pin to ground to disable the internal voltage regulators. 10 6 6 ecg1_la analog input, left arm (la) . 11 5 5 ecg2_ll analog input, left leg (ll). 12 4 4 ecg3_ra analog input, right arm (ra) . 13 3 3 ecg4_v1 analog input, chest electrode 1 or auxiliary biopotential input (v1) . 14 2 2 ecg5_v2 analog input, chest electrode 2 or auxiliary biopotential input (v2) . notes 1. nc = no connect. do not connect to this pin. dgnd iovdd gpio0 gpio1 gpio2 gpio3 dgnd cs drdy sdi sclk sdo iovdd dgnd nc nc dgnd dvdd sync_gang pd reset adcvdd agnd agnd avdd vreg_en nc cal_dac_in nc avdd nc nc p i n 1 ad as1000-2 64-lead lqfp top view (not to scale) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 45 46 4 7 48 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 nc nc refgnd refout refin ecg1 ecg2 nc agnd ecg4 nc agnd nc ecg5 nc ecg3 nc avdd agnd agnd adcvdd nc nc dgnd clk_in cm_in avdd nc dvdd nc nc rld_sj 09660-010 notes 1. the exposed paddle is on the top of the package; it is connected to the most negative potential, agnd. 2. nc = no connect. do not connect to this pin. pin 1 indicator 1 agnd 2 nc 3 nc 4 nc 5 nc 6 refgnd 7 refout 8 refin 9 ecg1 10 ecg2 11 ecg3 12 ecg4 13 ecg5 14 agnd 35 36 37 38 39 40 41 42 34 33 32 31 30 29 15 avdd 16 cm_in 17 nc 19 nc 21 agnd 20 avdd 22 agnd 23 adcvdd 24 nc 25 nc 26 clk_in 27 dvdd 28 dgnd 18 rld_sj 45 sync_gang 46 pd 47 reset 48 adcvdd 49 agnd 50 agnd 51 avdd 52 vreg_en 53 nc 54 cal_dac_in 44 dvdd 43 dgnd adas1000-2 56-lead lfcsp top view (not to scale) 55 nc 56 avdd dgnd cs drdy sdi sclk sdo iovdd dgnd gpio3 gpio2 gpio1 gpio0 iovdd dgnd 09660-009 rev. b | page 15 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet adas1000 adas1000 - 1 adas1000 - 2 mnemonic description lqfp lfcsp lfcsp lqfp lfcsp 10 6 ecg1 analog input 1 . 11 5 ecg2 analog input 2 . 12 4 ecg3 analog input 3 . 13 3 ecg4 a nalog input 4 . 14 2 ecg5 analog input 5 . 4 12 ext_resp_ra opti onal external respiration input . 5 11 ext_resp_ll optional external respiration input . 6 1 0 ext_resp_la optional external respiration input. 62 16 respdac_ll optional path fo r higher performance r espiration re solution, r espiration dac drive, negative side 0 . 60 18 shield / respdac_la shared pin (user - configured ). output of shield driver (shield) . optional path for higher performance respiration resolution, respiration dac drive , negative side 1 (respdac_la) . 3 13 respdac_ra optional path for higher performance respiration resolution, respiration dac drive, positive side. 22 52 52 cm_out/wct common - mode output voltage (average of selected electrodes ). not intended to drive current. 19 55 55 19 55 cm_in co mmon - mode input . 21 53 53 21 53 rld_sj summing junction for right leg drive amplifier . 20 54 54 rld_out output and feedback junction for right leg drive amplifier . 61 17 17 cal_dac_io calibration dac input/outp ut. output for a m aster device, i nput for a s lave. not intended to drive current. 9 7 7 9 7 refin reference input . f or standalone mode , use refout connected to refin. external 10 f with esr < 0.2 in parallel with 0.1 f bypass capacitors to gnd are re quired and must be placed as close to the pin as possible . an external reference can be connected to refin. 8 8 8 8 8 refout reference output . 7 9 9 7 9 refgnd reference ground. connect to a clean ground. 27, 28 47, 46 47, 46 xtal1, xtal2 external cry stal connects between these two pins; apply external clock drive to clk_io . each xtal pin requires 15 pf to ground. 29 45 45 clk_io buffered clock i nput /o utput . output for a m aster device ; i nput for a slave . powers up in high impedance. 41 35 35 41 3 5 cs chip select and frame sync, active low . cs can be used to frame each word or to frame the entire suite of data in framing mode. 44 32 32 44 32 sclk clock input . data is clocked into the shift register on a rising edge and clocked out on a falling edge . 43 33 33 43 33 sdi serial data input . 53 25 25 53 25 pd power - down, active low . 45 31 31 45 31 sdo serial data output . this pin is used for reading back register configuration data and for the d ata frames. 42 34 34 42 34 drdy digital output. this pin indicates that conversion data is ready to be read back when low, busy when high. when reading packet data, the entire packet must be read to allow drdy to retur n high. 54 24 24 54 24 reset digital input . this pin has an internal pull - up. t his pin resets all intern al nodes to their power - on reset values. 52 26 26 52 26 sync_gang digital input/output (output on master, input on slave). used for synchronization control where multiple devices are connected together. powers up in high impedance. 36 40 40 gpio0/ mcs general - purpose i/o or master 128 khz spi cs . 37 39 39 gpio1/msclk general - purpose i/o or mast er 128 khz spi sclk . 38 38 38 gpio2/msdo general - purpose i/o or master 128 khz spi sdo . 39 37 37 gpio3 general - purpose i/o. rev. b | page 16 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 adas1000 adas1000 - 1 adas1000 - 2 mnemonic description lqfp lfcsp lfcsp lqfp lfcsp 1, 16, 17, 32, 33, 48, 49, 64 10, 11, 12, 13, 16 1, 3, 4, 5, 6, 16, 17, 20, 22, 27, 28, 32, 33, 48, 49, 60, 62, 64 10, 11, 1 2, 13, 16, 18, 46, 47, 52, 54 nc no connect . d o not connect to these pins (see figure 7 , figure 9 , figure 10 , and figure 11). 36 40 gpio0 general - purpose i/o. 37 39 gpio1 general - purpose i/o. 38 38 gpio2 general - purpose i/o. 39 37 gpio3 general - purpose i/o. 18 shield output of shield driver. 61 17 cal_dac_in calib ration dac input. input for companion device. calibration signal comes from the master. 29 45 clk_in buffered clock input. drive t his pin from the master clk_io pin. 57 57 57 epad exposed pad. the exposed paddle is on the top of the package; it is c onnected to the most negative potential, agnd. rev. b | page 1 7 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet typical performance characteristics figure 12 . input referred noise for 0.5 hz to 40 hz bandwidth, 2 khz data rate, gain 0 (1.4) figure 13 . input refe rred noise for 0.5 hz to 40 hz bandwidth, 2 khz data rate, gain 3 (4.2) figure 14 . input referred noise for 0.5 hz to 150 hz bandwidth, 2 khz data rate, gain 0 (1.4) figure 15 . input referred nois e for 0.5 hz to 150 hz bandwidth, 2 khz data rate, gain 3 (4. 2 ) figure 16 . ecg channel noise performance over a 0.5 hz to 40 hz or 0.5 hz to 150 hz bandwidth vs. gain setting figure 17 . typical gai n error across channels ?6 ?4 ?2 0 2 4 6 8 input referred noise ( v) time (seconds) 0.5hz to 40hz gain setting 0 = 1.4 data rate = 2khz 10 seconds of data 0 1 2 3 4 5 6 7 8 9 10 09660-039 ?6 ?4 ?2 0 2 4 6 8 input referred noise ( v) time (seconds) 0.5hz to 40hz gain setting 3 = 4.2 data rate = 2khz 10 seconds of data time (seconds) 0 1 2 3 4 5 6 7 8 9 10 09660-040 ?15 ?10 ?5 0 5 10 15 input referred noise ( v) 0.5hz to 150hz gain setting 0 = 1.4 data rate = 2khz 10 seconds of data time (seconds) 0 1 2 3 4 5 6 7 8 9 10 09660-041 ?15 ?10 ?5 0 5 10 15 input referred noise ( v) 0.5hz to 150hz gain setting 3 = 4.2 data rate = 2khz 10 seconds of data time (seconds) 0 1 2 3 4 5 6 7 8 9 10 09660-042 0 5 10 15 20 25 gain 0 gain 1 gain 2 gain 3 input referred noise ( v) gain setting la 150hz la 40hz 09660-043 0.010 0.012 0.014 0.016 0.018 0.020 la ll ra v1 v2 gain error (%) avdd = 3.3v gain setting 0 = 1.4 09660-044 electrode input rev. b | page 18 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 18 . typical gain error vs. gain figure 19 . typical gain error for all gain settings across temperature figure 20 . typical ecg channel lea kage current over input voltage range vs. temperature figure 21 . dc lead - off comparator low threshold vs. temperature figure 22 . dc lead - off comparator high threshold vs. temperature figure 23 . filter response with 40 hz filter enabled , 2 khz data rate; s ee figure 75 for digital filter overview 0.001 0.021 0.041 0.061 0.081 0.101 0.121 gain 0 gain 1 gain 2 gain 3 gain error (%) avdd = 3.3v 09660-045 gain setting ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?40 ?20 0 20 40 60 80 gain error (%) temper a ture (c) gain error g0 gain error g1 gain error g2 gain error g3 avdd = 3.3v gain setting 0 = 1.4 gain setting 1 = 2.1 gain setting 2 = 2.8 gain setting 3 = 4.2 09660-046 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0.3 0.8 1.3 1.8 2.3 leakage (na) vo lt age (v) +85 c +55 c +25 c ?5 c ?40 c avdd = 3.3v gain setting 0 = 1.4 09660-047 0.180 0.185 0.190 0.195 0.200 0.205 0.210 0.215 ?40 ?20 0 20 40 60 80 threshold (v) temper a ture (c) ecg dc lead-off threshold rld dc lead-off threshold avdd = 3.3v 09660-048 2.375 2.380 2.385 2.390 2.395 2.400 2.405 2.410 2.415 2.420 ?40 ?20 0 20 40 60 80 high threshold (v) temper a ture (c) ecg dc lead-off threshold rld dc lead-off threshold avdd = 3.3v 09660-049 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 10 100 1k gain (db) frequenc y (hz) avdd = 3.3v 09660-050 rev. b | page 19 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet figure 24 . filter response with 150 hz filter enabled , 2 k hz data rate; see figure 75 for digital filter overview figure 25 . filter response with 250 hz filter enabled , 2 khz data rate; see figure 75 for digital filter overview figure 26 . filter response with 450 hz filter enabled , 2 khz data rate ; see figure 75 for digital filter overview figure 27 . a nalog channel bandwidth figure 28 . filter response running at 128 khz data rate ; see figure 75 for digital filter overview figure 29 . typical internal vref vs. temperature ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 10 100 1k frequenc y (hz) gain (db) avdd = 3.3v 09660-051 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 10 100 1k frequenc y (hz) gain (db) 09660-052 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequenc y (hz) 1 10 100 1k gain (db) avdd = 3.3v 09660-053 ?6 ?5 ?4 ?3 ?2 ?1 0 frequenc y (hz) 1 10 100 1k 10k 100k gain (db) avdd = 3.3v 09660-054 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequenc y (hz) gain (db) 1 10 100 1k 10k 100k avdd = 3.3v 09660-055 1.7965 1.7970 1.7975 1.7980 1.7985 1.7990 1.7995 1.8000 1.8005 1.8010 ?40 ?20 0 20 40 60 80 vo lt age (v) temper a ture (c) 09660-056 rev. b | page 20 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 30 . vcm_ref vs. temperature figure 31 . typical avdd supply current vs. temperature , using internal advcdd/dvdd supplies figure 32 . typical avdd su pply current vs. temperature , using externally supplied advcdd/dvdd figure 33 . typical avdd supply current vs. temperature in standby mode figure 34 . typical avdd supply current vs. avdd supply volt age figure 35 . respiration with 200 m impedance variation , using internal respiration paths and measured with a 0 patient cable temper a ture (c) 1.2970 1.2975 1.2980 1.2985 1.2990 1.2995 1.3000 1.3005 1.3010 ?40 ?20 0 20 40 60 80 vo lt age (v) avdd = 3.3v 09660-057 temper a ture (c) 12.20 12.25 12.30 12.35 12.40 12.45 12.50 ?40 ?20 0 20 40 60 80 a vdd supp l y current (ma) avdd = 3.3v 5 ecg channels enabled internal ldo utilized high performance/low noise mode 09660-060 temper a ture (c) 3.395 3.400 3.405 3.410 3.415 3.420 3.425 3.430 ?40 ?20 0 20 40 60 80 a vdd supp l y current ( ma) avdd = 3.3v 5 ecg channels enabled adcvdd and dvdd supplied externally high performance/low noise mode 09660-058 765 770 775 780 785 790 795 800 805 ?40 ?20 0 20 40 60 80 a vdd supp l y current ( a) temper a ture (c) avdd = 3.3v 09660-069 12.35 12.40 12.45 12.50 12.55 12.60 12.65 3.0 3.5 4.0 4.5 5.0 5.5 6.0 current (ma) volt age (v) low noise/high performance mode 09660-059 0.142925 0 5 10 15 20 25 30 0.142930 0.142935 0.142940 0.142945 0.142950 0.142955 respir a tion magnitude (v) time (seconds) avdd = 3.3v ecg path/defib/cable impedance = 0 ? patient impedance = 1k ? respiration rate = 10resppm respamp = 11 = 60 a p-p respgain = 0011 = 4 09660-062 rev. b | page 21 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet figure 36 . respiration with 100 m impedance variation , using inte rnal respiration paths and measured with a 0 patient cable figure 37 . respiration with 200 m impedance variation , using internal respiration paths and measured with a 5 k patient cable figure 38 . respiration with 200 m impedance variation , using external respiration dac driving 100 pf external capacitor and measured with a 0 patient cable figure 39 . respiration with 200 m impedance variation , using external resp iration dac driving 100 pf external capacitor and measured with a 5 k patient cable figure 40 . respiration with 200 m impedance variation , using external respiration dac driving 1 nf external capacitor and measured with a 1. 5 k patient cable figure 41 . respiration with 100 m impedance variation , using external respiration dac driving 1 nf external capacitor and measured with a 1.5 k patient cable 0 5 10 15 20 25 30 time (seconds) 0.121115 0.121120 0.121125 0.121130 0.121135 0.121140 0.121145 respiration magnitude (v) avdd = 3.3v ecg path/defib/cable impedance = 0? patient impedance = 1k? respiration rate = 10resppm respamp = 11 = 60a p-p respgain = 0011 = 4 09660-063 0 5 10 15 20 25 30 0.663130 0.663135 0.663140 0.663145 0.663150 0.663155 0.663160 respir a tion magnitude (v) time (seconds) avdd = 3.3v ecg path/defib/cable impedance = 5k ? patient impedance = 1k ? respiration rate = 10resppm respamp = 11 = 60a p-p respgain = 0011 = 4 09660-064 0 5 10 15 20 25 30 time (seconds) 0.062335 0.062340 0.062345 0.062350 0.062355 0.062360 0.062365 respir a tion magnitude (v) avdd = 3.3v ecg path/defib/cable impedance = 0? patient impedance = 1k? extcap = 100pf respiration rate = 10resppm respamp = 11 = 60a p-p respgain = 0011 = 4 09660-065 0 5 10 15 20 25 30 time (seconds) respir a tion magnitude (v) 0.517360 0.517365 0.517370 0.517375 0.517380 0.517385 0.517390 avdd = 3.3v ecg path/defib/cable impedance = 5k ? /250pf patientimpedance = 1k ? extcap = 100pf respiration rate = 10resppm respamp = 11 = 60 a p-p respgain = 0011 = 4 09660-067 0 5 10 15 20 25 30 time (seconds) 0.159745 0.159750 0.159755 0.159760 0.159765 0.159770 0.159775 respir a tion magnitude (v) time (seconds) avdd = 3.3v ecg path/defib/cable impedance = 1.5k ? /600pf patient impedance = 1k ? extcap = 1nf respiration rate = 10resppm respamp = 11 respgain = 0001 = 1 09660-066 0 5 10 15 20 25 30 time (seconds) 0.159 1 18 0.159 1 19 0.159120 0.159121 0.159122 0.159123 0.159124 0.159125 0.159126 respir a tion magnitude (v) extcap= 1nf respiration rate = 10resppm respamp = 11 respgain = 0001 = 1 09660-068 avdd = 3.3v ecg path/defib/cable impedance = 1.5k?/600pf patient impedance = 1k ? rev. b | page 22 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 42 . dnl vs . input voltage range across electrode s at 25c figure 43 . dnl vs. input voltage range across temperature figure 44 . inl vs. input voltage across gain setting for 2 khz data rate figure 45 . inl vs. input voltage across electrode channel for 2 k hz data rate figure 46 . inl vs. input voltage across gain setting for 16 khz data rate figure 47 . inl vs. input voltage a cross gain setting for 128 khz data rate ?50 ?20 ?30 ?40 ?10 0 20 10 30 40 50 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) dn l error ( v rti) avdd = 3.3v la ll ra v1 v2 09660-070 ?50 ?20 ?30 ?40 ?10 0 20 10 30 40 50 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) dn l error ( v rti) avdd = 3.3v ?4 0 c ?5c +25c +55c +85c 09660-071 ?150 ?100 ?50 0 50 100 150 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) in l ( v/rti) gain0 gain1 gain2 gain3 avdd = 3.3v 09660-073 ?150 ?100 ?50 0 50 100 150 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) in l ( v/rti) avdd = 3.3v la ll ra v1 v2 09660-074 ?100 ?50 0 50 100 150 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) in l ( v/rti) avdd = 3.3v gain0 gain1 gain2 gain3 09660-075 ?150 ?100 ?50 0 50 100 150 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 input vo lt age (v) in l ( v/rti) avdd = 3.3v gain0 gain1 gain2 gain3 09660-076 rev. b | page 23 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet figure 48 . fft with 60 hz input signal figure 49 . snr and thd across gain settings figure 50 . power up avdd line to drdy going low (ready) figure 51 . open - loop gain response of adas1000 right leg drive amplifier without loading figure 52 . open - loop phase response of adas1000 right leg drive amplifier without loading ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 amplitude (dbfs) frequenc y (hz) avdd = 3.3v gain 0 data rate = 2khz filter setting = 150hz 09660-077 ?100 ?50 0 50 100 150 gain 0 gain 1 gain 2 gain 3 amplitude (db) gain setting snr thd avdd = 3.3v ?0.5dbfs 10hz input signal 09660-078 ch1 2.00v m1.00ms a ch1 2.48v t 22.1% ch2 1.00v 2 1 09660-079 drdy avdd = 3.3v avdd 120 loo p gain (db) 100 80 60 40 20 0 ?20 ?40 ?60 ?80 frequenc y (hz) 100m 1 10 100 1k 1g 10k 100k 1m 10m 100m 09660-080 0 loo p gain (phase) ?350 ?300 ?250 ?200 ?150 ?100 ?50 frequenc y (hz) 100m 1 10 100 1k 1g 10k 100k 1m 10m 100m 09660-081 rev. b | page 24 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 applications informa tion overview the adas1000 / adas1000 - 1 / adas1000 - 2 are electro cardiac (ecg) front - end solution s targeted at a variety of medical appli - cations. in addition to ecg measurements, the adas1000 version also measures th oracic impedance (respiration) and detects pacing ar tifacts , providing all the measured information to the host controller in the form of a data frame supplying either lead/vector or el ectrode data at programmable data rates. the adas1000 / adas1000 - 1 / adas1000 - 2 are designed to simplify the task of acquiring ecg signals for use in both monitor and diagnostic applications. value - added cardiac post processing can be executed externally on a dsp, microprocessor , or fpga. the adas1000 / adas1000 - 1 / adas1000 - 2 are designed for operation in both low power , portable telemetry applications and line powered systems ; therefore , the parts offer power/noise scaling to ensure suitability to these varying requiremen ts. the device s also offer a suite of dc and ac test excitation via a calibration dac feature and crc redund ancy checks in addition to read back of all relevant register address space. figure 53 . adas1000 simplified block diagram ? + rld_sj driven lead amp shield drive amp shield ecg1_la ecg2_ll ecg3_ra ecg4_v1 ecg5_v2 rld_out cm_in vref refout xtal1 xtal2 pd cs sclk sdi dgnd sdo drdy reset agnd iovdd clock gen/osc/ external clk source sync_gang refin cal_dac_io respiration path ext_resp_la ext_resp_ll dc lead- off/muxes vcm_ref (1.3v) ac lead-off dac respiration dac calibration dac clk_io avdd adcvdd dvdd gpio3 gpio1/msclk gpio2/msdo gpio0/mcs amp amp ecg path vref filters, control, and interface logic ext_resp_ra respdac_la respdac_ll respdac_ra mux refgnd cm_out/wct 10k ? adcvdd, dvdd 1.8v regulators adas1000 10k ? vcm amp adc adc adc amp adc amp adc amp adc ? + ac lead-off detection pace detection common- mode amp 09660-0 1 1 rev. b | page 25 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet figure 54 . adas1000 - 1 simplified block diagram common- mode amp r l d_sj driven lead amp shield drive amp shield e c g 1 _ l a e c g 2 _ ll e c g 3 _ r a e c g 4 _ v 1 e c g 5 _ v 2 ac lead-off detection r l d_out cm_in vref refout x t a l1 x t a l2 pd cs sclk sdi d g n d sdo drdy reset a g n d iovdd clock gen/osc/ external clk source sync_gang refin c a l _d a c _io dc lead- off/muxes vcm_ref (1.3v) calibration dac clk_io avdd adcvdd dvdd gpio3 gpio1/msclk gpio2/msdo gpio0/mcs amp amp ecg path vref filters, control, and interface logic ref g n d cm_out/wct 10k? adcvdd, dvdd 1.8v regulators adas1000-1 10k? vcm adc adc amp adc amp adc amp adc ac lead-off dac 09660-012 rev. b | page 26 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 55 . adas1000 - 2 slave device simplified block diagram r l d_sj ecg1 ecg2 ecg3 ecg4 e c g 5 ac lead-off detection cm_in vref refout pd cs sclk sdi d g n d sdo drdy reset a g n d iovdd sync_gang refin c a l _d a c _in dc lead- off/muxes avdd adcvdd dvdd gpio3 gpio1 gpio2 gpio0 amp amp ecg path vref filters, control, and interface logic ref g n d 10k ? adcvdd, dvdd 1.8v regulators adas1000-2 10k ? adc adc amp adc amp adc amp adc common- mode amp ac lead-off dac 09660-013 rev. b | page 27 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet ecg inputs electrodes/leads the adas1000 / adas1000 - 1 / adas1000 - 2 ecg product consists of 5 ecg inputs and a reference drive, rld (right leg drive). in a typical 5 - lead /vector application , four of the ecg inputs ( ecg3_ ra, ecg1_ la, ecg2_ ll, ecg4_ v1) are used in addition to the rld pa th. this leaves one spare ecg path ( which can be used for other purposes, such as calibration or temperature measurement ) . both v1 and v2 input channels can be used for alternative measurements , if desired . when used in this way, the negative terminal of t he input stage can be switched to the fixed internal vcm _ref = 1.3 v; see detail s in table 50. in a 5 - lead system, the adas1000 / adas1000 - 1 / adas1000 - 2 can provide lead i, lead ii, an d lead iii data or electrode data directly via the serial interface at all frame rates . the other ecg leads can be calculated by the users software from either the l ead data or the e lectrode data provided by the adas1000 / adas1000 - 1 / adas1000 - 2 . note that in 128 khz data rate, lead data is only available when configured in analog lead mode , as shown in figure 58. digital lead mode is not available for this data rate. a 12- lead (10 - ele ctrode) system c a n be achieved using one adas1000 or adas1000 - 1 device ganged together with one adas1000 - 2 slave device as described in the gang mode operation section . here, 9 ecg e lectrodes and one rld electrode achieve the 10 electrode system, again leaving one spare ecg channel that c an be used for alternate purposes as suggested previously . in such a system, having nine dedicated electrodes benefits the user by delivering lead in formation based on electrode measurement s and calculation s rather than deriving leads from other lead measurements. table 10 outlines the calculation of the leads (vector) from the individual electrode measuremen ts. table 10 . lead composition 1 lead name composition equivalent adas1000 or adas1000 -1 i la C ra ii ll C ra iii ll C la avr 2 ra C 0.5 (la + ll) ? 0.5 (i + ii) avl 2 la C 0.5 (ll + ra) 0.5 (i ? iii) avf 2 ll C 0.5 (la + ra) 0.5 (ii + iii) v 1 v1 C 0.333 (la + ra + ll) v 2 v2 C 0.333 (la + ra + ll) 12 leads achieved by adding adas1000 -2 slave v 3 v3 C 0.333 (la + ra + ll) v 4 v4 C 0.333 (la + ra + ll) v 5 v5 C 0.333 (la + ra + ll) v 6 v6 C 0.333 (la + ra + ll) 1 these lead composit ions apply when the master adas1000 device is configured into l ead mode (analog lead mode or digital lead mode) with vcm = wct = (ra + la + l l)/3. when configured for 12 - lead ope ration with a master and slave device, the vcm signal derived on the master device (cm_out) is applied to the cm_in of the slave device. for correct operation of the slave device, the device must be configured in electrode mode (see the frmctl register in table 37) . 2 these augmented l ead s are not calcula ted within the adas1000 , but can be derived in the host dsp/microcontroller/fpga. rev. b | page 28 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 ecg channel the ecg channel consists of a programmable gain , low noise , differential preamplifier ; a fixed gain anti - aliasing filter ; buffers ; and an adc (see figure 56) . each elect rode input is routed to its pga noninverting input. internal switches allow the inverting inputs of the pga to be connected to oth er electrodes and/or the wilson central terminal (wct) to provide differential analog processing ( analog lead mode ), to a computed average of some or all electrodes, or the internal 1.3 v common - mode reference (vcm_ref). the latter two modes support digit al lead mode ( l eads computed on - chip) and e lectrode mode ( l eads calculated off - chip). in all cases , the internal reference level is removed from the final lead data. the adas1000 / adas1000 - 1 / adas1000 - 2 implementation uses a d c - coupled approach, which requires that the front end be biased to operate within the limited dynamic range imposed by the relatively low supply voltage . the right leg drive loop performs this function by forcing the electrical average of all selected elec trodes to the internal 1.3 v level, vcm_ref, maximizing each channels available signal range. all ecg channel amplifiers use chopping to minimize 1/f noise contributions in the ecg band. the chopping frequency of ~250 khz is well above the bandwidth of a ny signals of interest. the 2 - pole anti - aliasing filter has ~65 khz bandwidth to support digital pace detection while still providing greater than 80 db of attenuation at the adcs sample rate. the adc itself is a 14 - bit , 2 mhz sar converter; 1024 oversa mpling helps achieve the required system performance. the full - scale input range of the adc is 2 vref, or 3.6 v, although the analog portion of the ecg channel limits the useful signal swing to about 2.8 v. the adas1000 contains flags to indicate whether the adc data is out of range, indicating a hard electrode off state. programmable over range and underrange thresholds are shown in the loffuth and lofflth registers ( see table 39 and table 40 , respectively). the adc out of range flag is contained in the header word (see table 54). figure 56 . simplified schematic of a single ecg channel a d c f s 1 4 to common-mode amplifier for driven leg and shield driver shield driver a v d d vref electrode preamp g = 1, 1.5, 2, 3 filter diff amp buffer g = 1.4 patient cable adas1000 external rfi and defib protection vcm + ? electrode electrode external rfi and defib protection 09660-014 rev. b | page 29 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet electrode/lead forma tion and input stage configuration the input stage of the adas1000 / adas1000 - 1 / adas1000 - 2 can be arranged in several different manners. the input amplifi - ers are differential amplifiers and can be configured to generate the leads in the analog domain, before the adcs. in addition to this, the digital data can be configured to provide either electrode or lead format under user control as described in table 37 . this allows maximum flexibility of the input stage for a variety of applications. analog lead mode and calculation leads are con figured in the analog input stage when chconfig = 1, as shown in figure 58 . this uses a traditional in - amp structure where lead formation is performed prior to digitiza tion, with wct created using the common - mode amplifier. while this results in the inversion of lead ii in the analo g domain, this is digitally corrected so output data have the proper polarity. digital lead mode and calculation when the adas1000 / adas1000 - 1 / adas1000 - 2 are configured for digital lead mode (see the frmctl register, registe r 0x0a[4], table 37 ), the digital core calculates each lead from the electrode signals. this is straightforward for lead i/ lead ii/lead iii. calculating v1 and v2 requires wct, which is also computed internally for this purpose. this mode ignores the common - mode configuration specified in the cmrefctl register ( register 0x05). digital lead cal culation is only available in 2 khz and 16k hz data rates (see figure 59) . elec trode mode: single - ended input electrode configuration in this mode, the electrode data are digitized relative to the common - mode signal, vcm, which can be arranged to be any combination of the contributing ecg electrodes. common - mode generation is control led by the cmrefctl register as described in table 32 (see figure 61 ). electrode mode: common electrode a and electrode b configuration s in this mode, all electrodes are d igitized relative to a common electrode, for example , ra. standard leads must be calculated by post processing the output da ta of the adas1000 / adas1000 - 1 / adas1000 - 2 (s ee figure 60 an d figure 62) . figure 57 . electrode and lead configurations mode comment word1 word2 word3 word4 word5 common electrode (ce) leads (here ra electrode is connected to the ce electrode (cm_in) and v3 is on ecg3 input) lead i (la ? ra) lead ii (ll ? ra) v3? (v3 C ra) ? (la ? ra) ? (ll ? ra) v1? (v1 ? ra) ? (la ? ra) + (ll ? ra) v2? (v2 ? ra) ? (la ? ra) + (ll ? ra) analog lead lead i (la ? ra) lead ii (ll ? ra) lead iii (ll ? la) v1? (v1 ? vcm) v2? (v2 ? vcm) single-ended input electrode relative to vcm ll ? vcm leads formed relative to a common electrode (ce) la ? ce ll ? ce v1 ? ce v2 ? ce lead i (la ? ra) lead ii (ll ? ra) lead iii (ll ? la) v1? (v1 ? wct 4 ) v2? (v2 ? wct 4 ) single-ended input, digitally calculated leads common electrode a analog lead single-ended input electrode common electrode b digital lead 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 la ? vcm v3 ? ce ra ? vcm v1 ? vcm v2 ? vcm 09660-061 3 3 3 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. 4 wilson central terminal (wct) = (ra + la + ll)/3, this is a digitally calculated wct based on the ra, la, ll measurements. rev. b | page 30 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 58 . electrode and lead configurations , analog lead mode figure 59 . electrode and lead configurations, digital lead mode vcm = wct = (la + ll + ra)/3 c o mmo n - mo d e a mp ec g 1_ l a ec g 2_ l l ec g 3_ r a ec g 4_ v1 ec g 5_ v2 a mp ad c ad c ad c ad c ad c c m_ i n for example r a common electrode ce in + ? c m_ o u t / w c t l ead i (l a ? ra ) l ead ii i (ll ? l a ) l ead i i (ll ? ra )* v1 ? = v1 ? w c t v 2? = v 2 ? w c t wct = (l a + l l + ra)/3 w c t = ( la + ll + ra) / 3 * g e t s m u l i t p l e d b y ?1 i n d igi t a l a mp + ? a mp + ? a mp + ? a mp + ? mode comment word1 word2 word3 word4 word5 analog lead lead i (la ? ra) lead ii (ll ? ra) lead iii (ll ? la) v1? (v1 ? vcm) v2? (v2 ? vcm) analog lead 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 0 1 0 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. 09660-015 c o mm o n - m o d e a mp a mp ad c ad c ad c ad c ad c c m _ i n for example, r a c o mm o n e l e c t r o d e c e i n + ? c m _ o u t / w c t v1 ? wct v 2 ? wct a mp + ? a mp + ? a mp + ? a mp + ? e c g 1_ l a e c g 2_ l l e c g 3_ r a e c g 4_ v1 e c g 5_ v2 lead i l a ? r a lead ii l l ? r a lead iii l l ? l a v c m = w c t = ( l a + l l + ra ) / 3 mode comment word1 word2 word3 word4 word5 lead i (la ? ra) lead ii (ll ? ra) lead iii (ll ? la) v1? (v1 ? wct 4 ) v2? (v2 ? wct 4 ) single-ended input, digitally calculated leads digital lead 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 0 0 0 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. 4 wilson central terminal (wct) = (ra + la + ll)/3, this is a digitally calculated wct based on the ra, la, ll measurements. 09660-016 digital domain calculations rev. b | page 31 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet figure 60 . electrode and lead configurations, common electrode a figure 61 . electrode and lead configurations, single - ended input electrode v c m = r a c o mm o n - m o d e a mp a mp ad c ad c ad c ad c ad c c m _ i n = r a c o mm o n e l e c t r o d e c e i n + ? c m _ o u t / w c t a mp + ? a mp + ? a mp + ? a mp + ? e c g 1_ l a e c g 2_ l l e c g 3_ ra = v3 e c g 4_ v1 e c g 5_ v2 mode comment word1 word2 word3 word4 word5 common electrode (ce) leads (here ra electrode is connected to the ce electrode (cm_in) and v3 is on ecg3 input) lead i (la ? ra) lead ii (ll ? ra) v3? (v3 C ra) ? (la ? ra) ? (ll ? ra) v1? (v1 ? ra) ? (la ? ra) + (ll ? ra) v2? (v2 ? ra) ? (la ? ra) + (ll ? ra) common electrode a 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 0 0 1 09660-017 3 3 3 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. l ead i l ead ii v3? v1? v 2 ? digital domain calculations vcm = ( la+ l l + r a + v1)/ 4 in this case c o mm o n - m o d e a mp a mp ad c ad c ad c ad c ad c cm_in for example, r a c o mm o n e l e c t r o d e c e i n + ? cm_out/wct l a ? v c m ll ? v c m ra ? v c m v 1 ? v c m v 2 ? v c m vcm common mode can be an y combin a tion of electrodes a mp + ? a mp + ? a mp + ? a mp + ? ecg1_l a ecg 2_l l ecg3_r a ecg4_v1 ecg5_v2 mode comment word1 word2 word3 word4 word5 single-ended input electrode relative to vcm ll ? vcm single-ended input electrode 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 1 0 0 la ? vcm ra ? vcm v1 ? vcm v2 ? vcm 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. 09660- 1 18 rev. b | page 32 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 figure 62 . electrode and lead configurations, common electrode b vcm = ce = r a c o mmo n - mo d e a mp a mp ad c ad c ad c ad c ad c c m_ i n = r a c o mmo n el ec t r o d e c e i n + ? c m_ o u t / w c t l a ? r a ll ? r a v3 ? r a v1 ? r a v2 ? r a a mp + ? a mp + ? a mp + ? a mp + ? ec g 1_ l a ec g 2_ l l ec g 3_ ra = v3 ec g 4_ v1 ec g 5_ v2 mode comment word1 word2 word3 word4 word5 leads formed relative to a common electrode (ce) la ? ce ll ? ce v1 ? ce v2 ? ce common electrode b 0x0a [4] 1 0x01 [10] 2 0x05 [8] 3 1 0 1 v3 ? ce 09660-119 1 register frmctl, bit datafmt: 0 = lead/vector mode; 1 = electrode mode. 2 register ecgctl, bit chconfig: 0 = single ended input (digital lead mode or electrode mode); 1 = differential in p ut (analog lead mode). 3 register cmrefctl, bit cerefen: 0 = ce disabled; 1 = ce enabled. rev. b | page 33 of 80
adas1000/adas1000-1/adas1000-2 data sheet rev. b | page 34 of 80 defibrillator protection the adas1000 / adas1000-1 / adas1000-2 do not include defibrillation protection on chip. any defibrillation protection required by the application requires external components. figure 63 and figure 64 show examples of external defibrillator protection, which is required on each ecg channel, in the rld path and in the cm_in path if using the ce input mode. note that, in both cases, the total ecg path resistance is assumed to be 5 k. the 22 m resistors shown connected to rld are optional and used to provide a safe termination voltage for an open ecg electrode; they may be larger in value. note that, if using these resistors, the dc lead-off feature works best with the highest current setting. esis filtering the adas1000 / adas1000-1 / adas1000-2 do not include electrosurgical interference suppression (esis) protection on chip. any esis protection required by the application requires external components. ecg path input multiplexing as shown in figure 65, signal paths for numerous functions are provided on each ecg channel (except respiration, which only connect to the ecg1_la, ecg2_ll, and ecg3_ra pins). note that the channel enable switch occurs after the rld amplifier connection, thus allowing the rld to be connected (re-directed into any one of the ecg paths). the cm_in path is treated the same as the ecg signals. figure 63. possible defibrillation protection on ecg paths using neon bulbs figure 64. possible defibrillation protection on ecg paths using diode protection figure 65. typical ecg channel input multiplexing 09660-018 electrode patient cable 4k ? ecg1 500 ? 500 ? electrode patient cable 4k ? ecg2 rld 22m ? 1 22m ? 1 argon/neon bulb argon/neon bulb 1 optional. sp724 avdd sp724 avdd 500 ? 500 ? adas1000/ adas1000-1/ adas1000-2 electrode patient cable 4.5k ? adas1000/ a das1000-1/ adas1000-2 500 ? electrode patient cable 4.5k ? 500 ? rld 22m ? 1 22m ? 1 avdd avdd 1 optional. 2 two littelfuse sp724 channels per electrode may provide best protection. sp724 2 sp724 2 ecg1 ecg2 09660-019 analog lead (ra/la/ll) input amplifier rld amp dclo current aclo current 11.3pf respiration input caldac channel enable ecg pin 1.3v vcm_ref + ? to cm averaging from cm averaging to filtering adas1000 vcm mux for lead config, common electrode + ? 09660-020
data sheet adas1000/adas1000-1/adas1000-2 rev. b | page 35 of 80 common-mode selection and averaging the common-mode signal can be derived from any combina- tion of one or more electrode channel inputs, the fixed internal common-mode voltage reference, vcm_ref, or an external source connected to the cm_in pin. one use of the latter arrangement is in gang mode where the master device creates the wilson central terminal for the slave device or devices. the fixed reference option is useful when measuring the calibration dac test tone signals or while attaching electrodes to the patient, where it allows a usable signal to be obtained from just two electrodes. the flexible common-mode generation allows complete user control over the contributing channels. it is similar to, but independent of, circuitry that creates the right leg drive (rld) signal. figure 66 shows a simplified version of the common-mode block. if the physical connection to each electrode is buffered, these buffers are omitted for clarity. there are several restrictions on the use of the switches: ? if sw1 is closed, sw7 must be open. ? if sw1 is open, at least one electrode switch (sw2 to sw7) must be closed. ? sw7 can be closed only when sw2 to sw6 are open, so that the 1.3 v vcm_ref gets summed in only when all ecg channels are disconnected. the cm_out output is not intended to supply current or drive resistive loads, and its accuracy is degraded if it is used to drive anything other than the slave adas1000-2 devices. an external buffer is required if there is any loading on the cm_out pin. figure 66. common-mode generation block table 11. truth table for common-mode selection ecgctl address 0x01 1 cmrefctl address 0x05 2 pwren drvcm extcm lacm llcm racm v1cm v2cm on switch description 0 x x x x x x x powered down, paths disconnected 1 x 0 0 0 0 0 0 sw7 internal vcm_ref = 1.3 v is selected 1 0 0 1 0 0 0 0 sw2 internal cm selection: la contributes to vcm 1 0 0 1 1 0 0 0 sw2, sw3 internal cm selection: la and ll contribute to vcm 1 0 0 1 1 1 0 0 sw2, sw3, sw4 internal cm selection: la, ll, and ra contribute to vcm (wct) . . . . . . . . . . 1 x 1 x x x x x sw1 external vcm selected 1 see table 28. 2 see table 32. ecg1_la ecg2_ll ecg3_ra ecg4_v1 ecg5_v2 + ? cm_in adas1000 sw2 vcm_ref = 1.3v sw3 sw6 sw5 sw4 sw1 sw7 cm_out vcm (when selected, it gets summed in on each ecg channel) 09660-021
adas1000/adas1000 - 1/adas1000 - 2 data sheet w ilson central termin al (wct) the flexibility of the common - mode selection averaging allows the user to achieve a wilson central terminal voltage from the ecg1_la, ecg2_ll, ecg3_ra electrodes . right leg drive/refe rence drive the right leg drive amplifier or reference amplifier is used as part of a feedback loop to force the patient s common - mode voltage close to the i nternal 1.3 v reference level ( vcm _ref ) of the adas1000 / adas1000 - 1 / adas1000 - 2 . this centers all the electrode inputs relative to the input span, providing maximum input dynamic range. it also helps to reject noise and inter ference from external sources such as fluorescent lights or other patient - connected instruments, and absorbs the dc or ac lead - o ff c urrents injected on the ecg electrodes. the rld amplifier c a n be used in a variety of ways as shown in figure 67 . its input can be taken from the cm_out signal using an external resistor. alternatively, some or all of the electrode signals can be combined using the internal switches. the dc gain of the rld amplifier is set by the ra tio of the external feedback resistor (rfb) to the effective input resistor, which can be set by an external resistor , or alternatively , a function of the number of selected electrodes as configured in the cmrefctl register (see table 32 ). in a typical case , using the internal resistors for r in , all active electrodes are used to derive the right leg drive, resu lt ing in a 2 k effective input resistor. achieving a typical dc gain of 40 db thus require s a 200 k feedback resistor. the dynamics and stability of the rld loop depend on the chosen dc gain and the resistance and capacitance of the patient cabling . in general, loop compensation using external components is require d, and must be determined experimentally for any given instrument design and cable set. in some cases, adding lead compensation proves necessary, while in others , lag compensation is more appropriate. the s umming junction of the rld amplifier is brought out to a package pin (rld_sj) to facilitate compensation. the short circuit current capability of the rld amplifier exceeds regulatory limits. a patient protection resistor is required to achieve compliance. within the rld block, there is lead - off comparator circuitry that monitors the rld amplifier output to determine whether the patient feedback loop is closed. an open - loop condition, typically the result of the right leg electrode (rld _out ) becoming detac hed, tend s to drive the output of the amplifier low. this type of fault is flagged in the header word ( see tabl e 54 ), allowing the system software to take action by notifying the user, redirecting the reference dri ve to another electrode via the internal switches of the adas1000 / adas1000 - 1 / adas1000 - 2 , or both. the detection circuitry is local to the rld amplifier and remain s functional with a redirected reference drive. table 32 provides details on reference drive redirection. whil e reference drive redirection can be useful in the event that the right leg electrode cannot be reattached, some precautions must be observed. most important is the need for a patient protection resistor. because this is an external resistor, it does not follow the redirected reference drive; some provision for continued patient protection is needed external to the adas1000 / adas1000 - 1 / ad as1000 - 2 . any additional resistance in the ecg paths certainly interfe re s with respiration measurement and may also result in an increase in noise and decrease in cmrr. the rld amplifier is designed to stably driv e a maximum capacitance of 5 nf based on the gain configuration ( see figure 67 ) and assuming a 330 k patient protection resistor . figure 6 7 . right leg drive possible external component configuration electrode la electrode ll electrode ra electrode v1 electrode v2 + ? sw2 cm_in or cm buffer out sw3 sw6 sw5 sw4 sw1 externally supplied components to set rld loop gain cz 2nf 40k ? r in * 4m ? rfb* 100k? rz vcm_ref (1.3v) rld_out rld_sj adas1000 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? rld_int_redirect cm_out/wct *external resistor r in is optional. if driving rld from the electrode paths, then the series resistance will contribute to the r in impedance. where sw1 to sw5 are closed, r in = 2k ? . rfb should be chosen accordingly for desired rld loop gain. 09660-022 rev. b | page 36 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 calibration dac within t he adas1000 / adas1000 - 1 , there are a number of cal ibration features. the 10 - bit calibration dac can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. the options are as follows: ? dc voltage output (range : 0.3 v to 2.7 v). the dac transfer function for dc voltage output is ( ) ? ? ? ? ? ? ? ? ? + 1 2 v 4 . 2 v 3 . 0 10 code ? 1 mv p - p sine wave of 10 hz or 150 hz ? 1 mv 1 hz square wave internal switching allow s the calibration dac signals to be routed t o the input of each ecg channel ( see figure 65) . alternatively, it can be driven out from the cal_dac_io pin, enabling measurement and correction for external error sources in the entire ecg signal chain and/or for use as an input to the adas1000 - 2 companion chip calibration input. to ensure a successful update of the calibration dac (see table 36 ), the host controller must issue four additional sclk cycles after writing the new calibration dac register word. gain calibration the gain for each ecg channel can be adjusted to correct for gain mismatches between channels. factory trimmed gain correction coefficients are stored in nonvolatile memory on - chip for gain 0, gain 1, a nd gain 2 ; there is no factory calibration for gain 3. the default gain values can be overwritten by user gain correction coefficients, which are stored in volatile memory and available by addressing the appropriate gain control registers ( see table 51 ) . the gain calibration applies to the ecg data available on the standard interface and applies to all data rates. lead -o ff detection an ecg system must be able to detect if an electrode is no longer connected to the patient. the adas1000 / adas1000 - 1 / adas1000 - 2 support two methods of lead - off detection, ac lead - off detection and dc lead - off detection. the two systems are independent and can be used singly or together under the control of the serial interface (see table 29). a lead - off event sets a flag in the frame header word (see table 54). identification of which electrode is off is available as part of the data frame or as a register read from the lead - off status register (register loff, see table 47 ). in the case of ac lead - off, infor - mation about the amplitude of the lead - off signal or signals can be read back through the serial interface (see table 52). in a typical ecg configuration, the electrodes ra, la, and ll are used to generate a common mode of wilson central terminal (wct). if one of these electrodes is off, this affects the wct signal and any lead measurements that it contributes to. as a result, the ecg measurements on these signals are expected to degrade. t he user has full control over the common mode amplifier and can adjust the common - mode configuration to remove that electrode from the common - mode generation. in this way, the user can continue to make measurements on the remaining connected leads. dc lead - off detection this method injects a small programmable dc current into each input electrode . when a n electrode is properly connected , the current flow s into the right leg (rl d_out ) and produce s a minimal voltage shift. if an electrode is off, the current charge s the capacitance of that pin , causing the voltage at the pin to float positive and create a l arge voltage change that is detected by the comparators in each channel. these comparators use fixed, gain - independent upper and lower threshold voltages of 2.4 v and 0.2 v, respectively. if the input exceeds either of these levels, the lead - off flag is ra ised. the lower threshold is included in the event that something pulls the electrode down to ground. the dc lead - o ff detection current can be programmed via the serial interface. typical currents range from 10 na to 70 na in 10 na steps. all input pins (r a, la, ll, v 1 , v 2 , and cm_in) use identical dc lead - off detection circuitry. detecting if the right - leg electrode has fallen off is necessarily different as rld_out is a low impedance amplifier output. a pair of fixed threshold comparators monitor the outp ut voltage to detect amplifier saturation that would indicate a lead - off condition. this information is available in the dclead - off register (register 0x1e) along with the lead - off status of all the input pins. the propagation delay for detecting a dc lead - off event depends on the cable capacitan ce and the programmed current. it is approximately delay = voltage c able capacitance / programmed current for e xample: delay = 1.2 v (200 pf/70 na) = 3.43 ms dc lead - off and high gains using dc lead - off at high ga ins can result in failure of the circuit to flag a lead - off condition. the chopping nature of the input amplifier stage contribute s to this situation. when the electrode is off, the electrode is pulled up; however, in this gain setting, the first stage amp lifier goes into saturation before the input signal crosses the dclo upper threshold, resulting in no lead - off flag. this affects the gain setting gain 3 (4.2) and partially gain 2 ( 2.8 ). rev. b | page 37 of 80
adas1000/adas1000-1/adas1000-2 data sheet rev. b | page 38 of 80 increasing the avdd voltage raises the voltage at which the input amplifiers saturate, allowing the off electrode voltage to rise high enough to trip the dclo comparator (fixed upper threshold of 2.4 v). the adas1000 operates over a voltage range of 3.15 v to 5.5 v. if using gain 2/gain 3 and dc lead-off, an increased avdd supply voltage (minimum 3.6 v) allows dc lead-off to flag correctly at higher gains. ac lead-off detection the alternative method of sensing if the electrodes are connected to the patient is based on injecting ac currents into each channel and measuring the amplitudes of the resulting voltages. the system uses a fixed carrier frequency at 2.039 khz, which is high enough to be removed by the adas1000 / adas1000-1 / adas1000-2 on-chip digital filters without introducing phase or amplitude artifacts into the ecg signal. figure 68. simplified ac lead-off configuration the amplitude of the signal is nominally 2 v p-p and is centered on 1.3 v relative to the chip agnd level. it is ac-coupled into each electrode. the polarity of the ac lead-off signal can be configured on a per-electrode basis through bits[23:18] of the loffctl register (see table 29). all electrodes can be driven in phase, and some can be driven with reversed polarity to minimize the total injected ac current. drive amplitude is also programmable. ac lead-off detection functions only on the input pins (la, ll, ra, v1, v2, and cm_in) and is not supported for the rld_out pin. the resulting analog input signal applied to the ecg channels is i/q demodulated and amplitude detected. the resulting amplitude is low pass filtered and sent to the digital threshold detectors. ac lead-off detection offers user programmable dedicated upper and lower threshold voltages (see table 39 and table 40). note that these programmed thresholds voltage vary with the ecg channel gain. the threshold voltages are not affected by the current level that is programmed. all active channels use the same detection thresholds. a properly connected electrode has a very small signal as the drive current flows into the right leg (rl), whereas a disconnected electrode has a larger signal as determined by a capacitive voltage divider (source and cable capacitance). if the signal measured is larger than the upper threshold, then the impedance is high, so a wire is probably off. selecting the appropriate threshold setting depends on the particular cable/ electrode/protection scheme, as these parameters are typically unique for the specific use case. this can take the form of starting with a high threshold and ratcheting it down until a lead-off is detected, then increasing the threshold by some safety margin. this gives simple dynamic thresholding that automatically compensates for many of the circuit variables. the lower threshold is added for cases where the only ac lead-off is in use and for situations where an electrode cable has been off for a long time. in this case, the dc voltage has saturated to a rail, or the electrode cable has somehow shorted to a supply. in either case, there is no ac signal present, yet the electrode may not be connected. the lower threshold checks for a minimum signal level. in addition to the lead-off flag, the user can also read back the resulting voltage measurement available on a per channel basis. the measured amplitude for each of the individual electrodes is available in register 0x31 through register 0x35 (loamxx registers, see table 52). the propagation delay for detecting an ac lead-off event is <10 ms. note that the ac lead-off function is disabled when the calibration dac is enabled. adc out of range when multiple leads are off, the input amplifiers may run into saturation. this results in the adc outputting out of range data with no carrier to the leads off algorithm. the ac lead-off algorithm then reports little or no ac amplitude. the adas1000 contains flags to indicate if the adc data is out of range, indicating a hard electrode off state. there are programmable overrange and under- range thresholds that can be seen in the loffuth and lofflth registers (see table 39 and table 40, respectively). the adc out of range flag is contained in the header word (see table 54). shield driver the shield drive amplifier is a unity gain amplifier. its purpose is to drive the shield of the ecg cables. for power consumption purposes, it can be disabled if not in use. note that the shield pin is shared with the respiration pin function, where it can be muxed to be one of the pins for external capacitor connection. if the pin is being used for the respiration feature, the shield function is not available. in this case, if the application requires a shield drive, an external amplifier connected to the cm_out pin can be used. respiration ( adas1000 model only) the respiration measurement is performed by driving a high frequency (programmable from 46.5 khz to 64 khz) differential current into two electrodes; the resulting impedance variation caused by breathing causes the differential voltage to vary at the respiration rate. the signal is ac-coupled onto the patient. the acquired signal is am, with a carrier at the driving frequency and a shallow modulation envelope at the respiration frequency. the modulation depth is greatly reduced by the resistance of the customer-supplied rfi and esis protection filters, in addition to the impedance of the cable and the electrode to skin interface (see table 12). the goal is to measure small ohm variation to sub ohm resolution in the presence of large series resistance. the circuit itself consists of a respiration dac that drives the ac- coupled current at a programmable frequency onto the chosen pair of electrodes. the resulting variation in voltage is amplified, ac lo dac 2.039khz 12.5na to 100na rms la ll ra v1 v2 09660-166 cm 11k ? 11k ? 11k ? 11k ? 11k ? 11k ?
data sheet adas1000/adas1000 - 1/adas1000 - 2 filtered , and synchronously demo dulated in the digital doma in; the result is a digital signal that represents the total thoracic or respiration impedance, including cable and electrode contri - b utions. while it is heavily low - pass filtered on - chip, the user is require d to further process it to extract the envelop e and perform the peak detection needed to establish breathing (or lack thereof). respiration measurement is available on one of the leads (lead i, lead ii, or lead iii ) or on an external path via a pair of dedicated pins ( ext_resp _la, ext_resp _ra , or ext_r esp _ll) . only one lead measurement can be made at one time. the respiration measurement path is not suited for use as addition al ecg measurements because the internal co nfiguration and demodulation do not align with an ecg measurement ; however , the ext_res p_la, ext_resp_ra, or ext_resp_ll paths can be multiplexed into one of the ecg adc paths , if required , as discussed in the extend switch on respiration paths section. the respiration signal processing path is not reconfigurable for ecg measurements, as it is specifically designed for the respiration signal measurement. table 12 . maximum allowable cable and thoracic loading cable resistance cable capacitance r < 1 k c < 1200 pf 1 k < r < 2.5 k c < 400 pf 2.5 k < r < 5 k c < 200 pf r thoracic < 2 k internal respiration capacitors the internal respiration function uses an internal rc network (5 k /100 pf) , and this circuit is capable of 200 m resolutio n ( with up to 5 k total path and cable impedance) . the current is ac - coupled onto the same pins that th e measurement is sensed back on . figure 69 shows the measurement on lead i, but , similarly , the measurement ca n be configured to measure on either lead ii or lead iii . the internal cap acitor mode requires no external capacitors and produces currents of ~ 64 a p - p amplitude when configured for max imum amplitude setting (1v) through the respctrl register (see table 30) . external respiration path the ext_resp_xx pins are provided for use either with the ecg electrode cables or, alternatively, with a dedicated external sensor independent of the ecg electrode path. additionall y, the ext_resp_xx pins are provided s o the user can measure the respiration signal at the patient side of any input filtering on the front end. in this case, the user must continue to take precautions to protect the ext_resp_xx pins from any signals appli ed that are in excess of the operating voltage range ( for example, esis or defib rillator signals). figure 69 . simplified respiration block diagram la cable ecg1_la ext_resp_la ecg2_ll ext_resp_ll ecg3_ra ext_resp_ra adas1000 oversampled 5k? 5k? 100pf 100pf respiration dac drive + 1v 1v cable and electrode impedance < 5k? ll cable ra cable filter filter filter respiration measure respiration dac drive? hpf in-amp and anti-aliasing magnitude and phase sar adc 09660-023 46.5khz to 64khz 46.5khz to 64khz lpf fc=10khz fc=150khz 7hz rev. b | page 39 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet external respiration capacitors if necessary, the adas1000 allows the user to connect external capacitors into the respiration circuit to achieve higher resolution (<200 m ). this level of resolution requires that the cable impedance be 1 k . the dia gram in figure 70 shows the connections at respdac_xx paths for the extended respiration configuration. again, the ext_resp_xx paths can be connected at the patient side of any filtering circuit; however, the user must provide protection for these pins. while this external capacitor mode requires external components, it can deliver a larger signal - to - noise ratio. note again that respiration can be measured on only one lead (at one time); therefore, only one pair of external respiration paths (and external capacitors) is required. if required, further improvements in respiration performance may be possible with the use of an instrumentation amplifier and op amp external to the adas1000 . the instrumentation amplifier must have sufficiently low noise performance to meet the target performance levels. this mode uses the external capacitor mode configuration and is shown in figure 71. bit 14 of the respctl register (address 0x03; see table 30 ) allows the user to bypass the on - chip amplifier when using an external instrumentation amplifier. f igure 70 . respiration meas urement using external capacitor figure 71 . respiration using external cap acitor and external amplifiers 1v 1v lpf la cable ecg1_la ext_resp_la ecg2_ll ext_resp_ll ecg3_ra ext_resp_ra adas1000 46.5khz to 64khz 46.5khz to 64khz oversampled 5k? 1k? 1k? 1k? 5k? 100pf 100pf fc=10khz fc=150khz 7hz respdac_la respdac_ra respdac_ll 1nf to 10nf 1nf to 10nf mutually exclusive mutually exclusive respiration dac drive + cable and electrode impedance < 1k? ll cable ra cable filter filter filter respiration measure respiration dac drive ? hpf in-amp and anti-aliasing magnitude and phase sar adc 09660-024 la cable adas1000 50khz to 56khz 46.5khz to 64khz oversampled 1k? 10k? 10k? 10k? 10k? 1k? 100? 100? respdac_la respdac_ra 1nf to 10nf 1nf to 10nf respiration dac drive + ve cable and electrode impedance < 1k? ra cable respiration measure respiration dac drive ? ve hpf in-amp and anti-aliasing magnitude and phase sar adc ext_resp_la ext_resp_ra refout = 1.8v 0 . 9 v gain 1/2 of ad8606 1/2 of ad8606 09660-025 1v 1v lpf fc=10khz fc=150khz 7hz rev. b | page 40 of 80
data sheet adas1000/adas1000-1/adas1000-2 rev. b | page 41 of 80 respiration carrier frequency the frequency of the respiration carrier is programmable and can be varied through the respctl register (address 0x03, see table 30). the status of the hp bit in the ecgctl register also has an influence on the carrier frequency as shown in table 13. table 13. control of respiration carrier frequencies. respaltfreq 1 respextsync 1 hp 2 resp- freq 1 respiration carrier frequency 0 0 1 00 56 0 0 1 01 54 0 0 1 10 52 0 0 1 11 50 0 0 0 00 56 0 0 0 01 54 0 0 0 10 52 0 0 0 11 50 1 0 1 00 64 1 0 1 01 56.9 1 0 1 10 51.2 1 0 1 11 46.5 1 0 0 00 32 1 0 0 01 28 1 0 0 10 25.5 1 0 0 11 23 1 control bits from respctl (register 0x03). 2 control bit from ecgctl (register 0x01). in applications where an external signal generator is used to develop a respiration carrier signal, that external signal source can be synchronized to the internal carrier using the signal available on gpio3 when bit 7, respextsel, is enabled in the respiration control register (see table 30). table 14. control of respiration carrier frequency available on gpio3 respalt- freq 1 respext- sync 1 hp 2 resp- freq 1 respiration carrier frequency on gpio3 0 x 3 x 3 xx 3 64 1 1 1 00 64 1 1 1 01 56 1 1 1 10 51.2 1 1 1 11 46.5 1 1 0 00 32 1 1 0 01 28 1 1 0 10 25.5 1 1 0 11 23 1 control bits from respctl (register 0x03). 2 control bit from ecgctl (register 0x01). 3 x = dont care. evaluating respiration performance ecg simulators offer a convenient means of studying the performance of the adas1000 . while many simulators offer a variable-resistance respiration capability, care must be taken when using this feature. some simulators use electrically programmable resistors, often referred to as digipots, to create the time-varying resistance to be measured by the respiration function. the capacitances at the terminals of the digipot are often unequal and code-dependent, and these unbalanced capacitances can give rise to unexpectedly large or small results on different leads for the same programmed resistance variation. best results are obtained with a purpose- built fixture that carefully balances the capacitance presented to each ecg electrode. extend switch on respiration paths there is additional multiplexing on the external respiration inputs to allow them to serve as additional electrode inputs to the existing five ecg adc channels. this approach allows a user to configure eight electrode inputs; however, it is not intended as a true 8-channel/12-lead solution. time overheads are required to reconfigure the multiplexer arrangement using the serial interface in addition to filter the latency as described in table 16. the user has full control over the sw1/sw2/sw3 configuration as outlined in table 50. figure 72. alternative use of the respiration paths to ecg1_la channel to ecg2_ll channel to ecg3_ra channel to ecg4_v1 channel to ecg5_v2 channel ext_resp_r a ext_resp_ll ext_resp_la sw1a sw1b sw1c sw1d sw1e sw2a sw2b sw2c sw2d sw2e sw3a sw3b sw3c sw3d sw3e to respiration circuitry 09660-032
adas1000/adas1000-1/adas1000-2 data sheet rev. b | page 42 of 80 pacing artifact detection function ( adas1000 only) the pacing artifact validation function qualifies potential pacing artifacts and measures the width and amplitude of valid pulses. these parameters are stored in and available from any of the pace data registers (address 0x1a, and address 0x3a to address 0x3c). this function runs in parallel with the ecg channels. digital detection is performed using a state machine operating on the 128 khz 16-bit data from the ecg decimation chain. the main ecg signals are further decimated before appearing in the 2 khz output stream so that detected pace signals are not perfectly time-aligned with fully-filtered ecg data. this time difference is deterministic and can be compensated for. the pacing artifact validation function can detect and measure pacing artifacts with widths from 100 s to 2 ms and with amplitudes of <400 v to >1000 mv. its filters are designed to reject heartbeat, noise, and minute ventilation pulses. the flowchart for the pace detection algorithm is shown in figure 74. the adas1000 pace algorithm can operate with the ac lead-off and respiration impedance measurement circuitry enabled. once a valid pace is detected in the assigned leads, the pace- detected flags appear in the header word (see table 54) at the start of the packet of ecg words. these bits indicate that a pace is qualified. further information on height and width of pace is available by reading the contents of address 0x1a (pacedata register, see table 44). this word can be included in the ecg data packet/frame as dictated by the frame control register (see table 37). the data available in the pacedata register is limited to seven bits total for width and height information; therefore, if more resolution is required on the pace height and width, this is available by issuing read commands of the pacexdata registers (address 0x3a to address 0x3c) as shown in table 53. the on-chip filtering contributes some delay to the pace signal (see the pace latency section). choice of leads three identical and independent state machines are available and can be configured to run on up to three of four possible leads (lead i, lead ii, lead iii, and avf) for pacing artifact detection. any necessary lead calculations are performed internally and are independent of ecg channel settings for output data rate, low-pass filter cutoff, and mode (electrode, analog lead, common electrode). these calculations take into account the available front-end configurations as detailed in table 15. the pace detection algorithm searches for pulses by analyzing samples in the 128 khz ecg data stream. the algorithm searches for a leading edge, a peak, and a trailing edge as defined by values in the paceedgeth, paceampth, and pacelvlth registers, along with fixed width qualifiers. the post-reset default register values can be overwritten via the spi bus, and different values can be used for each of the three pace detection state machines. some users may not want to use three pace leads for detection. in this case, lead ii is the vector of choice, because this lead is likely to display the best pacing artifact. the other two pace instances can be disabled if not in use. the first step in pace detection is to search the data stream for a valid leading edge. once a candidate edge is detected, the algorithm begins searching for a second, opposite-polarity edge that meets with pulse width criteria and passes the (optional) noise filters. only those pulses meeting all the criteria are flagged as valid pace pulses. detection of a valid pace pulse sets the flag or flags in the frame header register and stores amplitude and width information in the pacedata register (address 0x1a; see table 44). the pace algorithm looks for a negative or positive pulse. table 15. pace lead calculation 0x01 [10] 1 0x05 [8] 2 configuration 0x04 [8:3] 3 00 01 10 11 lead i (la ? ra) lead ii (ll ? ra) lead iii (ll ? la) avf (lead ii + lead iii)/2 0 0 digital leads la C ra ch1 ? ch3 ll C ra ch2 ? ch3 ll C la ch2 ? ch1 ll ? (la + ra)/2 ch2 ? (ch1 + ch3)/2 0 1 c ommon electrode lead a lead i ch1 lead ii ch2 lead ii C lead i ch2 ? ch1 lead ii ? 0.5 lead i ch2 ? 0.5 ch1 1 x analog leads le ad i ch1 lead ii ?ch3 lead iii ch2 lead ii ? 0.5 lead i ? ch3 ? 0.5 ch1 1 register ecgctl, bit chconfig, see table 28. 2 r egister cmrefctl, bit cerefen, see table 32. 3 r egister pacectl, bit pacexsel [ 1:0], see table 31.
data sheet adas1000/adas1000-1/adas1000-2 rev. b | page 43 of 80 detection algorithm overview the pace pulse amplitude and width varies over a wide range, while its shape is affected by both the internal filtering arising from the decimation process and the low pass nature of the electrodes, cabling, and components used for defibrillation and esis protection. the adas1000 provides user programmable variables to optimize the performance of the algorithm within the ecg system, given all these limiting elements. the default parameter values are probably not optimal for any particular system design; experimentation and evaluation are needed to ensure robust performance. figure 73. typical pace signal the first step in pace detection is to search the data stream for a valid leading edge. once a candidate edge is detected, the algorithm verifies that the signal looks like a pulse and then begins searching for a second, opposite polarity edge that meets the pulse width and amplitude criteria and passes the optional noise filters. only the pulses meeting all requirements are flagged as valid pace pulses. detection of a valid pace pulse sets the flag or flags in the frame header register and stores amplitude and width information in the pacedata register (address 0x1a; see table 34). the pace algorithm detects pulses of both negative and positive polarity using a single set of parameters by tracking the slope of the leading edge and making the necessary adjustments to internal parameter signs. this frees the user to concentrate on determining appropriate threshold values based on pulse shape without concern for pulse polarity. figure 74. overview of pace algorithm the three user controlled parameters for the pace detection algorithm are pace amplitude threshold (paceampth), pace level threshold (pacelvlth), and pace edge threshold (paceedgeth). paceampth pace width leading edge leading edge stop pacelvlth paceedgeth recharge pulse pace pulse 09660-027 no enable pace detection select leads flag pace detected trailing edge detected? start start pulse width timer start noise filters (if enabled) noise filter passed? pulse width > 100s and <2ms update registers with width and height no no yes yes yes start pace detection algorithm no find leading edge a > paceedgeth? yes no find end of leading edge b < pacelvl yes pace amplitude >paceampth no yes yes 09660-026
adas1000/adas1000 - 1/adas1000 - 2 data sheet pace edge threshold this programmable level (address 0x0e, see table 41 ) is used to find a leading edge, signifying the start of a potential pace pulse. a candidate edge is one in which the leading edge crosses a threshold paceedgeth from the recent baseline. paceedgeth can be assigned any value between 0 and 255. setting paceedgeth to 0 forces it to the value paceampth/ 2 (see equation). non - zero values give the following : paceedgeth setting = 16 2 gain vref n were n is the 8 - bit programmed paceedgeth value (1 n 255). vref is the adas1000 reference voltage of 1.8 v. gain is the programmed gain of the ecg channel. the minimum threshold for 1.4 gain is 19.6 v, while the maximum for the same gain setting is 5.00 m v. pace level threshold this programmable level (address 0x0f, see table 42 ) is used to detect when the leading edge of a candidate p ulse ends. in general, a pace pulse is not perfectly square, and the top, meaning the portion after the leading edge, may continue to increase slightly or droop back towards the baseline. pacelvlth defines an allowable slope for this portion of the candida te pulse, where the slope is defined as the change in value over an internally - fixed interval after the pace edge is qualified. pacelvlth is an 8 - bit , twos complement number. positive values represent movement away from the baseline (pulse amplitude is sti ll increasing) while negative values represent droop back towards the baseline. pacelvlth setting = 16 2 gain vref n w ere n is the 8 - bit programmed pacelvlth value ( ? 128 n 127) . vref is the adas1000 reference voltage of 1.8 v. gain is the programmed gain of the ecg c hannel. the minimum value for 1.4 gain is 9.8 v, while the maximum f or the same gain setting is 2.50 m v. an additional qualification step, performed after pacelvlth is satisfied, rejects pulses with a leading edge transition t ime greater than about 156 s. this filter improves immunity to motion and other arti facts and ca nnot be disabled. overly aggressive esis filtering causes this filter to disqualify valid pace pulses. in such cases, increasing the value of paceedgeth provides more robust pace pulse detection. although counterintuitive, this change forces a larger initi al deviation from the recent baseline before the pace detection algorithm starts, reducing the time until pacelvlth comes into play and shortening the ap parent leading edge transition. increasing the value of paceedgeth may require a reduction in paceampth . pace amplitude threshold this register (address 0x07, see table 34 ) sets the minimum valid pace pulse amplitude. paceampth is an unsigned 8 - bit number. the programmed height is given by: paceampth setting = 16 2 2 gain vref n w ere n is the 8 - bit programmed paceampth value (1 n 255) . vref is the adas1000 reference voltage of 1.8 v . gain is the progr ammed gain of the ecg chann el. the minimum threshold for 1.4 gain is 19.6 v, while the maximum for the same gain setting is 5.00 m v. paceampth is typically set to the minimum expected pace amplitude and must be larger than the value of paceedgeth. the default register setting of n = 0x24 results in 706 v for a g ain = 1 setting. an initial paceampth setting between 700 v and 1 mv provides a good starting point for both unipolar and biventricular pacing detection. values below 250 v are not recommended because they greatly increase s ensitivity to ambient noise from the patient. the amplitude may need to be adjusted much higher than 1 mv when other medical devices are connected to the patient. pace validation filters a candidate pulse that successfully passes the combined tests of pace edgeth, pacelvlth, and paceampth is next passed through tw o optional validation filters. these filters are used to reject sub - threshold pulses such as minute ventilation (mv) pulse and signals from inductively coupled implantable telemetry systems. these f ilters perform different tests of pulse sh ape using a number of samples. both filters are enabled by default; filter 1 is controlled by bit 9 in the pacectl register (see table 31 ) and filter 2 is controlled by bi t 10 in the same register. these filters are not available on a l ead by l ead basis; if enabled, they are applied to all l eads being used for pace detection. pace width filter a candidate pulse that successfully passe s the edge, amplitude, and noise filters is finally checked for width. when this final filter is enabled, it checks that the candidate pulse is between 100 s and 2 ms wide. when a valid pace width is detected, the width is stored. disabling this filter affects only the minimum width (100 s) det ermination; the maximum width detection portion of the filter is always active. this filter is controlled by the pacectl register, bit 11 (see table 31 ). rev. b | page 44 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 bi v entricular pacers as described previously , the pace algorithm expects the pace pulse to be less than 2 ms wide. in a p acer where both ventricles are paced, they can be paced simultaneously . w here they fall within the width and height limits programmed into the algorithm, a valid pace is flagged, but only o ne pace pulse may be visible. with the p ace width filter enabled, the p ace algorithm seeks pace pulse widths within a 100 s to 2 ms window. assuming that this filter is enabled and in a scenario where two ventricle pacer pulse s fire at slightly different times, resulting in the pulse showing in the lead as one large , wider pulse, a valid pace is flagged so long as the total width does not exceed 2 ms. pace d etection measurement s design verification of the adas1000 digital pace algorithm include s detection of a range of simulated pace signals in addition to using the adas1000 and evaluation board with one pacemaker device connected to various simulated loads (approximately 200 to over 2 k ) and covering the following 4 waveform corners. ? minimum pulse width (100 s ), minimum height (to <300 v) ? minimum pulse width (100 s), maximum height (up to 1.0 v ) ? maximum pulse width (2 ms), minimum height (to <300 v) ? maximum pulse width (2 ms), maximum height (up to 1.0 v) these scenarios passed with acceptable results. the use of the ac lead - off function had no obvious impact on the recorded pace height, width , or the ability of the pace detection algorithm to identify a pace pulse. the pace algorithm was also evaluated with the respiration carrier enabled; again , no differences in the threshold or pacer detect were noted from the carrier. while these experimen ts validate the pace algorithm over a confined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm. this can be performed in only the end system, using the system manufacturers specified cables and vali dation data set. evaluating pace dete ction performance ecg simulators offer a convenient means of studying the perfor - mance and ability of the adas1000 to capture pace signals ov er the range of widths and heights defined by the various regulatory standards. while the pace detection algorithm of the adas1000 is designed to conform to medical instrument st andards (pace widths of 100 s to 2.00 ms and with amplitudes of <400 v to >1000 mv), some simulators put out signals wider or narrower than called for in the standards. the pace detection algorithm has been designed to measure a maximum pace widths of 2 ms with a margin of 0.25 ms to allow for simulator variations. pace width the adas1000 is capable of measuring pace widths of 100 s to 2.00 ms. the measured pace width is avail able through the pacexdata registers. these registers have limited resolution. the minimum pace width is 101.56 s and the maximum is 2.00 ms. the pace detection algorithm always returns a width greater than what is measured at the 50% point, ensuring that the algorithm is capable of measuring a narrow 100 s pulse. a valid pulse width of 100 s is reported as 101.56 s. any valid pace pulses 2.00 ms and 2.25 ms are reported as 2.00 ms. pace latency the pace algorithm always examines 128 khz , 16- bit ecg data, regardless of the selected fra me rate and ecg filter setting. a pace pulse is qualified when a valid trailing edge is detected and is flagged in th e next available frame header. pace and ecg data is always correctly time - aligned at the 128 khz frame rate, but the additional filtering inherent in the slower frame rates delays the ecg data of the frame re lative to the pace pulse flag. these delays are summarized in table 16 and must be taken into account to ena ble correct positioning of the pace event relative to the ecg data. there is an inherent one - frame - period uncertainty in the exact location of the pace trailing edge. pace d etection via secondary serial i nterface ( adas1000 and adas1000 -1 o nly) the adas1000 / adas1000 - 1 provide a second serial interface for users who w ant to implement their own pace detec tion schemes. this interface is configured as a m aster interface. it provides ecg data at the 128 khz data rate only. the purpose of this interface is to allow the user to access the ecg data at a rate sufficient to allow them to run their own pace algorit hm , while maintaining all the filtering and decimation of the ecg data that the adas1000 / adas1000 - 1 offer on the standard serial interface (2 khz and 16 khz data rates). this dedicated p ace interface uses three of the four gpio pins, leaving one gpio pin available even when th e secondary serial interface is enabled. note that the on - chip digital calibration to ensure channel gain matching does not apply to data that is available on this interface. this interface is discussed in more detail in the secondary serial i nterface section . rev. b | page 45 of 80
adas1000/adas1000-1/adas1000-2 data sheet rev. b | page 46 of 80 filtering figure 75 shows the ecg digital signal processing. the adc sample rate is programmable. in high performance mode, it is 2.048 mhz; in low power mode, the sampling rate is reduced to 1.024 mhz. the user can tap off framing data at one of three data rates, 128 khz, 16 khz, or 2 khz. note that although the data-word width is 24 bits for the 2 khz and 16 khz data rate, the usable bits are 19 and 18, respectively. the amount of decimation depends on the selected data rate, with more decimation for the lower data rates. four selectable low-pass filter corners are available at the 2 khz data rate. filters are cleared by a reset. table 16 shows the filter latencies at the different data rates. figure 75. ecg channel filter signal flow table 16. relationship of ecg waveform to pace indication 1, 2, 3 data rate conditions apparent delay of ecg data relative to pace event 4 2 khz 450 hz ecg bandwidth 0.984 ms 250 hz ecg bandwidth 1.915 ms 150 hz ecg bandwidth 2.695 ms 40 hz ecg bandwidth 7.641 ms 16 khz 109 s 128 khz 0 1 ecg waveform delay is the time required to reach 50% of final value following a step input. 2 guaranteed by design, not subject to production test. 3 there is an unavoidable residual uncertainty of 8 s in determining the pace pulse trailing edge. 4 add 38 s to obtain the absolute delay for any setting. 2.048mhz a dc dat a 14-bits 2.048mhz 128khz ?3db at 13khz aclo carrier notch 2khz ac lead-off detection pace detection 128khz data rate 16-bits wide available data rate choice of 1: 40hz 150hz 250hz (programmable bessel ) ~7hz 16khz data rate 24-bits wide 18 usable bits 2khz data rate 24-bits wide 19 usable bits 128khz 16khz ?3db at 3.5khz 2khz ?3db at 450hz 16khz calibration 31.25hz data rate 24-bits wide ~22 usable bits 09660-028
data sheet adas1000/adas1000-1/adas1000-2 rev. b | page 47 of 80 voltage reference the adas1000 / adas1000-1 / adas1000-2 have a high performance, low noise, on-chip 1.8 v reference for use in the adc and dac circuits. the refout of one device is intended to drive the refin of the same device. the internal reference is not intended to drive significant external current; for optimum performance in gang operation with multiple devices, each device should use its own internal reference. an external 1.8 v reference can be used to provide the required vref. in such cases, there is an internal buffer pro- vided for use with external reference. the refin pin is a dynamic load with an average input current of approximately 100 a per enabled channel, including respiration. when the internal reference is used, the refout pin requires decoupling with a10 f capacitor with low esr (0.2 maximum) in parallel with 0.01 f capacitor to refgnd, these capacitors should be placed as close to the device pins as possible and on the same side of the pcb as the device. gang mode operation while a single adas1000 or adas1000-1 provides the ecg channels to support a five-electrode and one-rld electrode (or up to 8-lead) system, the device has also been designed so that it can easily extend to larger systems by paralleling up multiple devices. in this mode of operation, an adas1000 or adas1000-1 master device can easily be operated with one or more adas1000-2 slave devices. in such a configuration, one of the devices ( adas1000 or adas1000-1 ) is designated as master, and any others are designated as slaves. it is important that the multiple devices operate well together; with this in mind, the pertinent inputs/outputs to interface between master and slave devices have been made available. note that when using multiple devices, the user must collect the ecg data directly from each device. if using a traditional 12-lead arrangement where the vx leads are measured relative to wct, the user must configure the adas1000 or adas1000-1 master device in lead mode with the slave adas1000-2 device configured for electrode mode. the lsb size for electrode and lead data differs (see table 43 for details). in gang mode, all devices must be operated in the same power mode (either high performance or low power) and the same data rate. master/slave the adas1000 or adas1000-1 can be configured as a master or slave, while the adas1000-2 can only be config- ured as a slave. a device is selected as a master or slave using bit 5, master, in the ecgctl register (see table 28). gang mode is enabled by setting bit 4, gang, in the same register. when a device is configured as a master, the sync_gang pin is automatically set as an output. when a device is configured as a slave ( adas1000-2 ), the sync_gang and clk_io pins are set as inputs. synchronizing devices the ganged devices need to share a common clock to ensure that conversions are synchronized. one approach is to drive the slave clk_io pins from the master clk_io pin. alter- natively, an external 8.192 mhz clock can be used to drive the clk_io pins of all devices. the clk_io powers up high impedance until configured in gang mode. in addition, the sync_gang pin is used to synchronize the start of the adc conversion across multiple devices. the sync_gang pin is automatically driven by the master and is an input to all the slaves. sync_gang is in high impedance until enabled via gang mode. when connecting devices in gang mode, the sync_gang output is triggered once when the master device starts to convert. therefore, to ensure that the slave device or devices receive this synchronization signal, configure the slave device first for oper- ation and enable conversions, followed by issuing the conversion signal to the ecgctl register in the master device. figure 76. master/slave connections in gang mode, using multiple adas1000 / adas1000-1 / adas1000-2 devices calibration the calibration dac signal from one device (master) can be output on the cal_dac_io pin and used as the calibration input for other devices (slaves) when used in the gang mode of operation. this ensures that they are all being calibrated using the same signal which results in better matching across channels. this does not happen automatically in gang mode but, rather, must be configured via table 36. master clk_oi sync_gang cm_out cal_dac_io clk_io sync_gang cm_in cal_dac_io sync_gang cm_in slave 0 slave 1 cal_dac_io clk_io 09660-029
adas1000/adas1000 - 1/adas1000 - 2 data sheet c ommon mo de the adas1000 / adas1000 - 1 have a dedicated cm_ou t pin serving as an output and a cm_in pin as an input . in gang mode , the master device determine s the common - mode voltage based on the selected input electrodes . t his common - mode signal (on cm_out) can then be used by subsequent slave devices ( applied to cm_in) as the common - mode reference. all electrodes within the slave device are then measured with respect to th e cm_in signal from the master device. see the cmrefctl register in table 32 for more details on the c ontrol via the serial interface. figure 77 shows the connections between a master and slave device using multiple adas1000 / adas1000 - 2 devices . right leg drive the right le g drive comes from the m aster device. if the internal rld resistors of the slave device are to contribute to the rld loop, tie the rld_sj pi ns of master and slave together. sequencing devices into gang mode when entering gang mode with multiple devices, both devices can be configured for operation, but the conversion enable bit (ecgctl register , bit 2 , table 28 ) of the m aster device should be set after the conversion enable bit of the s lave device. when the m aster device c onversion signal is set, the master device generates one edge on its sync_gang pin . this applies to any s lave sync_gang inputs, allo wing the devices to sync hronize adc conversions. figure 77 . configuring multiple devices to extend number of electrodes/leads ( this example uses adas 1000 as master and adas1000 - 2 as slave . similarly the adas1000 - 1 could be use d as master . ) sync_gang take lead data take electrode data electrodes 5 vref refout refin cal_dac_io amp amp adc respiration path muxes ac lead-off dac adc 5 ecg path filters, control, and interface logic pace detection cs sclk sdi sdo drdy lead-off detection common- mode amp rld_sj driven lead amp shield drive amp shield rld_out cm_in x t a l1 x t a l2 iovdd clock gen/osc/ external clk source ext resp_la ext resp ll vcm_ref (1.3v) clk_io avdd adcvdd dvdd ext resp_ra cm_out/ wct ac lead-off dac 10k? adcvdd, dvdd 1.8v regulators (optional) (optional) adas1000 c a l _dac_in cm_in sync_gang electrodes 5 amp muxes adc 5 ecg path filters, control, and interface logic pace detection cs sclk sdi sdo drdy lead-off detection common- mode amp rld_sj iovdd clock gen/osc/ external clk source vcm_ref (1.3v) clk_io avdd adcvdd dvdd adcvdd, dvdd 1.8v regulators (optional) (optional) adas1000-2 slave calibration dac respiration dac vref refout refin 09660-030 rev. b | page 48 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 in terfacing in gang mo de as shown in figure 77 , when using multiple devices, the user must collect the ecg data directly from each device. the example shown in figure 78 ill ustrates one possibility of how to approach interfacing to a master and slave device. note that sclk, sdo, and sdi are shared here with individual cs lines. this requires the user to read the data on both devices twice as fast to ensure that they can capture all the data to maintain the chosen data rate and ensure they have the relevant synchronized data. alternative methods might use individual controllers for each device or separate sdo paths. for some applications, digital isolation is required between the host and the adas1000 . the example shown illustrates a means to ensure that the number of lines re quiring isolation is minimized. table 17 . some possible arrangements for gang operation master slave 1 slave 2 features number of electrodes number of leads adas1000 adas1000 -2 ecg, respiration, pace 10 ecg, cm_in, rld 12- lead + spare adc channel adas1000 adas1000 -2 adas1000 -2 ecg, respiration, pace 15 ecg, cm_in, rld 15- lead + 3 spare adc channels adas1000 adas1000 -3 ecg, respiration, pace 8 ecg, cm_in, rld 12- lead (derived leads) adas1000 -1 adas1000 -2 ecg 10 ecg, cm_in, rld 12- lead + spare adc channel adas1000 -3 adas1000 -2 ecg 8 ecg, cm_in, rld 12- lead (derived leads) adas1000 - 4 adas1000 - 2 ecg, respiration, pace 8 ecg, cm_in, rld 12 - lead (derived leads) figure 78 . one method of interfacing to multiple devices master sclk sdi cs sdo drdy (optional) sclk sdi cs2 sdo cs1 slave sclk sdi cs sdo drdy (optional) microcrontroller/ dsp 09660-031 rev. b | page 4 9 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet serial interface s the adas1000 / adas1000 - 1 / adas1000 - 2 are controlled via a standard serial interface allowing configuration of registers and readback of ecg data . t his i s an spi - compatible interface that ca n operate at sclk frequencies up to 40 mhz . the adas1000 / adas1000 - 1 also provide a n optional secondary serial interface that is capable of providing ec g data at the 128 khz data rate for user s wishing to apply their own digital pace detection algorithm . this is a m aster interface that operat es with an sclk of 20 .48 mhz. standard serial i nterface th e standard serial interface is lvttl - compatible when ope rating from a 2.3 v to 3.6 v io v dd supply. this is the primary interface for controlling the adas1000 / adas1000 - 1 / adas1000 - 2 , reading and writing registers , and reading frame d ata containing all the ecg data - words and other st atus functions within the device. the spi is controlled by the following five pins : ? cs (frame synchronization input) . asserting cs low selects the device. when cs is high, data on the sdi pin is ignore d. if cs is inactive, the sdo output driver is disabled, so that multiple spi devices can share a common sdo pin. the cs pin can be tied low to reduce the number of isolated paths required. when cs is t ied low, there is no frame around the data - words ; therefore , the user must be aware of where they are within the frame . all data - words with 2 khz and 16 khz data rates contain register addresses at the start of each word within the frame. user s can re synch ronize the interface by holding sdi high for 64 sclk cycles, followed by a read of any register so that sdi is brought low for the first bit of the following word. ? sdi (serial data input pin) : data on sdi is clocked into the device on the rising edges of sclk. ? sclk (clocks data in and out of the device) . scl k should idle high when cs is high. ? sdo (serial data output pin for data readback) . data is shifted out on sdo on the falling edges of sclk. the sdo output driver is h i gh - z when cs is high. ? drdy ( data ready, optional) . d a ta ready when low, busy when high . i ndicat es the internal status of the adas1000 / adas1000 - 1 / adas1000 - 2 digital logic. it is driven high /busy during reset. if data frames are enabled and the frame buffer is empty, this pin is driven busy/high. if the frame buffer is full, this pin is driven low /ready . if d ata frames are not enabled, this pin is driven low to indicate that the device is ready to accept register read/write commands. when reading packet data, the entire packet must be read to allow the drdy return back high. the host controller must treat the drdy signal as a level sensitive input. figure 79 . serial interface write mode t he serial word for a write is 32 bits long, msb first. the serial interface works with both a continuous and a burst (gated) serial clock. the falling edge of cs starts the write cycle. serial data applied t o sdi is clocked into the adas1000 / adas1000 - 1 / adas1000 - 2 on rising sclk edges. at least 32 rising clock edges must be applied to sclk to clock in 32 bits of data before cs is taken high again. the addressed input register is updated on the rising edge of cs . for another serial transfer to take place, cs must be taken low again. register writes are used to configure the device. once the device is configured and enabled for conversions, frame data can be initiated to start clocking out ecg data on sdo at the programmed data rate. normal operation for the device is to send out frames of ecg data. typically , r egister reads and writes are needed only during start - up configuratio n. however, it is possible to write new configuration data to the device while in framing mode. a new write command is accepted within the frame and , depending on the nature of the command, there may be a need to flush out the internal filters (wait period s) before seei ng usable framing data agai n. write/read data format address, data , and the read/write bit s are all in the same word. data is updated on the rising edge of cs or the first cycle of the following word. for all write commands to the adas1000 / adas1000 - 1 / adas1000 - 2 , the data - word is 32 bits , as shown in table 18 . similarly, when using data rates of 2 khz and 16 khz, each word is 32 bits (address bits and data bits). table 18 . serial bit assignment ( applies to all register writes , 2 khz and 16 khz reads ) b 31 [b 30:b 24] [b 23:b 0 ] r / w address bits[ 6:0 ] data bits [23:0] (msb first) for register rea ds, data is shifted o ut during the next word , as shown in table 19. table 19. write/read data stream digital pin command 1 command 2 command 2 sdi read addr ess 1 read address 2 write address 3 sdo address 1 read data 1 address 2 read data 2 microcontroller/ dsp adas1000 sclk sdi cs sdo drdy sclk mosi cs miso gpio 09660-033 rev. b | page 50 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 in the 128 khz data rate, all write words are still 32 - bit writes but the read words in the data packet are now 16 bits (upper 16 bits of register) . t here are no address bits, only data bits. register space that is lar ger than 16 bits span s ac ross 2 16- bit words (for example, pace and r espiration). data frames/packets the general data packet structure is shown in table 18 . data can be received in two different frame formats . for the 2 khz and 16 khz data rate s, a 32 - bit data format is used (where the register address is encapsulated in the upper byte , identifying the word within the frame) (s ee table 22 ). f or the 128 khz data rate, words are provided in 16 - bit data format (s ee table 23 ). when the configuration is complete, the user can begin reading frames by issuing a read command to the f rame header r egister ( see table 54 ). the adas1000 / adas1000 -1 / adas1000 -2 continue to make frames available until another register address is written (read or write command). to continue reading frame data, continue to write all zeros on sdi , which is a write of the nop register (address 0x00) . a frame is interrupted only when another read or write command is issued. each frame can be a large amount of data plus status words. cs can toggle between each word of data within a frame, or it can be held constantly low during the entire frame. by default , a frame contains 11 32 -b it words when reading at 2 khz or 16 khz data rates ; similarly , a frame contains 13 16 -b it words when reading at 128 khz. the default frame configur ation does not include the optional respiration phase word ; however , this word can be included as needed. additionally any words not required can be excluded from the frame. to arrange the frame with the words of interest, configure the appropriate bits in the f rame c ontrol r egister ( see table 37 ). the complete set of words per frame are 12 32 -b it words for the 2 khz or 16 khz data rates, or 15 16 -b it words at 128 khz. any data not available within the frame ca n be read between frames. reading a register interrupts the frame and requires the user to issue a new read command of address 0x40 ( see table 54 ) to start framing again. read mode although the primary reading fun ction within the adas1000 / adas1000 -1 / adas1000 -2 is the output of the ecg frame data, the device s also allow reading of all configuration regis - ters. to read a register, the user must first address the device with a read comm and containing the particular register address. if the device is already in data framing mode, the read register command can be interle aved between the frames by issuing a read register command during the last word of frame data. data shifted out during th e next word is the register read data. to return to f raming mode, the user must re - enable framing by issuing a read of the frame header register (address 0x40 ; see table 54) . t his register write can be used to flush out the register contents from the previous read command. table 20 . example of reading registers and frames sdi .. nop read address n read f rames nop nop .. sdo .. frame d ata frame crc register data n frame h eader frame data .. regular register reads are always 32 bits long and msb first. serial clock rate the sclk can be up to 40 mhz , depending on the iovdd voltage level as shown in table 5 . the minimum sclk frequency is set by the requirement that all frame data be clocked out before the next frame becomes available . sclk (min) = frame_rate words_per_frame bits_per_word the minimum sclk for the various frame rates is show n in table 21 . table 21 . sclk clock frequency v s. packet data/frame rates frame rate word size maximum words/frame 1 min imum sclk 128 khz 16 bits 15 words 30.72 mhz 16 khz 32 bits 12 words 6.14 mhz 2 khz 32 bits 12 words 768 khz 1 this is the full set of words that a frame contains. it is programmable and can be configured to provide only the words of interest. see t able 37. table 22. default 2 khz and 16 khz data rate : 32- bit frame word format register header lead i/la lead ii/ll lead iii/ra v1/v1 v2/v2 pace respm respph loff gpio crc address 0x40 0x11 0x12 0x13 0x14 0x15 0x1a 0x1b 0x1 c 0x 1d 0x06 0x41 table 23. default 128 khz data rate : 16- bit frame word format 1 register header lead i/la lead ii/ll lead iii/ra v1/v1 v2/v2 pace1 pace2 respm1 respm2 loff gpio crc address 0x40 0x11 0x12 0x13 0x14 0x15 0x1a 0x1b 0 x1d 0x06 0x41 1 respiration phase words (2 16- bit words) are not shown in this frame, but can be included. rev. b | page 51 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet internal operations are synchronized to the internal master clock at either 2.048 mhz or 1.024 mhz (ecg c tl[3]: hp = 1 and hp = 0, respectively , see table 28). because there is no guaranteed relat ionship between the internal clock and the sclk signal of the spi , an internal handshaking scheme is used to ensure safe data transfer between the two clock domains. a full handshake requires three internal clock cycles and imposes an upper speed limit on the sclk frequency when reading frames with small word counts . this is true for all data frame rates. sclk ( max ) = (1.024 mhz (1 + hp ) words_per_frame bits_per_word )/3 ; or 40 mhz , whichever is lower. exceeding the maximum sclk frequency for a partic ular operating mode ca u se s erratic behavior in the drdy signal and result s in the loss of data. data rate and skip mode although the standard frame rates available are 2 khz, 16 khz , and 128 khz, there is also a provision to skip frames to further reduce the data rate. this can be configured in the frame control regist er (see table 37) . data ready ( drdy ) the drdy pin is used to indicate that a frame composed of decimated data at the selected data rate is available to read. i t is high wh en busy and low when ready. send c ommands only when the status of drdy is low or ready. during power - on, the status of drdy is high ( busy ) whil e the device initializes itself. when initialization is complete, drdy goes low and the user can start configuring the device for operation. when the device is config - ured and enabled for conversions by writing to the conversion bit (cnve n) in the ecgctl register, the adcs start to convert and the digital interface starts to make data available, loading them into the buffer when ready. if conversion s are enabled and the buffer is empty, the device is not ready and drdy go es high. once the buffer is full, drdy goes low to indicate that data is ready to be read out of the device. if the device is not enabled for conversion s , the drdy ignores the state of the buffer full status. when readi ng packets of data, the entire data packet must be read; otherwise , drdy stay s low. there are three methods of detecting drdy status. ? drdy pin . this is an output pin from the adas1000 / adas1000 - 1 / adas1000 - 2 that indicates the device read or busy status . no data is valid while this pin is high. the drdy signals that data is ready to be read by driving low and remaining low until the entire frame has been read. it is cleared when the last bit of the last word in the frame is clocked onto sdo. th e use of this pin is optional. ? sdo pin. the user can monitor the voltage level of the sdo pin by bringing cs low. if sdo is low, data is ready ; if high, busy. this does not require clocking the sclk input. (cph a = cpol = 1 only). ? one of t he first bit s of valid data in the header word available on sdo is a data ready status bit (s ee table 43) . within the configuration of the adas1000 / adas1000 - 1 / adas1000 - 2 , the user can set the header to repeat until the data is ready . see bit 6 ( rd y rpt ) in the frame control r egister in table 37. the host controller must read the entire frame to ensure drdy returns low and ready. if the host controller treats the drdy as an edge triggered signal and then misses a frame or underruns, the drdy remains high because there is still data available to read. the host controller must treat the drdy signal as level triggered, ensuring that whenever it goes low, it generates a n interrupt which can initiate a spi frame transfer. on completion of the transfer the drdy returns high. detecting missed conversion data to ensure that the current data is valid, the entire frame must be read at the selected data rate. if a read of the entire frame takes longer than the selected data rate allows , the internal buffer is not loaded with the latest conversion data . the frame header register ( see table 54) provides four settings to indicate an overflow of frame data. the settings of bits[29:28] report how many frames have been missed since the last valid frame read . a missed frame may occur as a result of the last read taking too long. the data in the current frame is valid data, but it is not the current data . i t is the calculation made directly after the last valid read. to cle ar such an overflow, the user must read the entire frame. rev. b | page 52 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 crc word framed data integrity is provided by crcs. for the 128 khz frame rates, the 16 - bit crc - cci tt polynomial is used. for the 2 khz and 16 khz frame rates, the 24 - bit crc polynomial used . in both cases, the crc residue is preset to all 1s and inverted before being transmitted. the crc parameters are summarized in table 24. to verify that data i s correctly received, software computes a crc on both the data and the received checksum. if data and checksum are received correctly, the resulting crc residue equals the check constant shown in table 24 . note that data is shifted through the generator polynomial msb first, the same order that it is shifted out serially. the bit and byte order of the crc that is appended to the frame is such that the msb of the crc is shifted th rough the generator polynomial first in the same order as the data so that the crc residue xor d with the inverted crc at the end of the frame is all 1s , which is why the check constan t is identical for all messages . the crc is based only on the data that is sent out. figure 80 . input clock clocks the adas1000 / adas1000 - 1 / adas1000 - 2 run from an external crystal or clock input frequency of 8.192 mhz. the external clock input is provided for use in ga ng mode so conversions between the two devices are synchronized. in this mode, the clk_io pin is an output from the master and an input from the slave. to reduce power, t he clk_io is disabled when not in gang mode. all features within the adas1000 are a function of the frequency of the externally applied clock. using a frequency other than the 8.192 mhz previously noted cause s scaling of the data rates, filter corners, ac lead off frequency, r espiration frequency , and pace algorithm corners accordingly. table 24 . crc polynomials frame rate crc size polynomial poly nomial in hex check constant 2 khz , 16 khz 24 bits x 24 + x 2 2 + x 20 + x 19 + x 1 8 + x 1 6 + x 1 4 + x 13 + x 11 + x 10 + x 8 + x 7 + x 6 + x 3 + x 1 + x 0 0x 15d 6 dcb 0x 15a 0ba 128 khz 16 bits x 16 + x 12 + x 5 + x 0 0x 11021 0x 1d 0f xtal1 xtal2 adas1000 clk_io 09660-034 rev. b | page 53 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet secondary serial int erface this second serial interface is an optional interface that can be used for the user s own pace detection purposes. this interface contains ecg data at 128 khz data rate only. if using this interface, the ecg data is still available on the standard interface discussed previously at lower rates with all the decimation and filtering applied. if this interface is inactive, it draws no power. data is available in 16 - bit words , msb first . this interface is a m aster interface, with the adas1000 / adas1000 -1 providing the sclk, cs , sdo. is it shared across some of the existing gpio pins as follows: ? gpio1/msclk ? gpio0/ mcs ? gpio 2 /msdo this interface can be enabled via the gpio register ( see table 33 ). figure 81 . master spi interface for external pace detection purposes the data format of the frame starts with a header word and five ecg data - words , as shown in table 25, and completes with the same crc word as documented in table 24 for the 128 khz rate. all words are 16 bits. msclk run s at approximately 20 mhz and mcs is asser ted for the entire frame with the data available on msdo on the falling edge of msclk. msclk idles high when mcs is deasserted. the data format for this interface is fixed and not influenced by the frmctl register settings. all seven wor ds are output, even if the individual channels are not enabled. the header word consists of four bits of all 1 s followed by a 12- bit sequence counter. this sequence counter increments after every frame is sent, thereby allowing the user to tell if any fra mes have been missed and how many. reset there are two methods of resetting the adas1000 / adas1 000 -1 / adas1000 -2 to power - on default. bringing the reset line low or setting the swrst bit in the ecgctl register ( table 28) resets the contents of all internal registers to their power - on reset state. the falling edge of the reset pin initiates the reset process; drdy goes high for the duration, returning low when the reset process is complete . this sequence takes 1.5 m s maximum. do not write to the serial interface while drdy is high handling a reset command. when drdy returns low, normal operation resumes and the status of the reset pin is ignored until it goes low again. software reset using the swrst bit (see tabl e 28 ) requires that a nop ( no operation) command be issued to complete the reset cycle. pd function the pd pin p owers down all functions in low power mode. the digital registers maintain their contents. the power - down function is also available via the serial interface (ecg control register , see table 28 ). table 25 . master spi frame format; all words are 16 bits mode/ word 1 2 3 4 5 6 7 electrode mode 1 header ecg 1_la ecg 2_ll ecg 3_ra ecg 4_v1 ecg 5_v2 crc analog l ead mode 1 he ader lead i lead iii - lead ii (ra -ll) v1 v2 crc 1 as set by the frmctl register data datafmt, bit [4], see table 37 . adas1000 master spi sclk cs mcs/gpio0 microcontroller/ dsp msdo/gpio2 miso/gpio msclk/gpio1 09660-035 rev. b | page 54 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 spi output frame str ucture (ecg and status data) three data rates are offered for reading ecg data : low speed 2 khz / 16 khz rate s for e lectrode/ lead data (32 - bit words) and a high speed 128 khz for elect rode/lead data (16 - bit words). figure 82 . output frame structure for 2 khz and 16 khz data rates with sdo data configured for electrode or lead data figure 83 . output frame structure for 128 khz data r ate with sdo data configured for electrode data ( the 128 khz data rate can provide single - ended electrode data or analog lead mode data only . digital lead m ode is not available at 128 khz data rate . ) cs 1 sclk sdo 2 drdy 1 cs may be used in one of the following ways: a) held low all the time. b) used to frame the entire packet of data. c) used to frame each individual 32-bit word. 2 super set of frame data, words may be excluded. 32-bit data words 2 6 5 4 7 3 pace detection v1?/v1 lead iii/ra v2?/v2 lead i/la lead ii/ll 1 header respiration magnitude gpio 9 10 8 driven output data stream each sclk word is 32 clock cycles another frame of data crc word 11 lead-off 09660-036 cs 1 sclk sdo 2 2 6 5 4 7 3 v1 ra v2 la ll 1 header respiration magnitude drdy 9 11 10 8 driven output data stream another frame each sclk word is 16 clock cycles 16-bit data words pace 12 gpio crc word 1 cs may be used in one of the following ways: a) held low all the time. b) used to frame the entire packet of data. c) used to frame each individual 16-bit word. 2 super set of frame data, words may be excluded. lead-off 13 09660-037 rev. b | page 55 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet spi register definit ions and m emory map in 2 khz and 16 khz data rates, data takes the form of 32 - bit words. bit a6 to bit a0 serve as word identifiers. each 32 - bit word has 24 bits of data. a third high speed data rate is also offered : 128 khz with data in the form of 16- bit words (all 16 bits as data) . tabl e 26 . spi register memory map r /w 1 a[ 6 :0] d[23:0] register name table register description reset value r 0x00 xxxxxx nop nop ( n o operation) 0x000000 r/w 0x01 dddddd ecgctl table 28 ecg control 0x000000 r/w 0x02 dddddd loffctl table 29 lead - off control 0x000000 r/w 0x03 dddddd respctl table 30 respiration control 2 0x000000 r/w 0x04 dddddd pacectl table 31 pace detection control 0x000f88 r/w 0x05 dddddd cmrefctl table 32 common - mode , reference , and shield drive control 0xe00000 r/w 0x06 dddddd g pioctl table 33 gpio control 0x000000 r/w 0x07 dddddd paceampth table 34 pace amplitude threshold 2 0x242424 r/w 0x08 d ddddd testtone table 35 test tone 0x000000 r/w 0x09 dddddd caldac table 36 calibration dac 0x002000 r/w 0x0a dddddd frmctl tab le 37 frame control 0x079000 r/w 0x0b dddddd filtctl table 38 filter control 0x000000 r/w 0x0c dddddd loffuth table 39 ac l ead - off upper threshold 0x00ffff r/w 0x0d dddddd lofflth table 40 ac l ead - off lower threshold 0x000000 r/w 0x0e dddddd paceedgeth table 41 pace edge threshold 2 0 x000000 r/w 0x0f dddddd pacelvlth table 42 pace level threshold 2 0x000000 r 0x11 xxxxxx ladata table 43 la or lead i da ta 0x000000 r 0x12 xxxxxx lldata table 43 ll or lead ii data 0x000000 r 0x13 xxxxxx radata table 43 ra or lead iii data 0x000000 r 0x14 xxxxxx v1data table 43 v1 or v1 data 0x000000 r 0x15 xxxxxx v2data table 43 v2 or v2 data 0x000000 r 0x1a xxxxxx pacedata table 44 read pace detection dat a/status 2 0x000000 r 0x1b xxxxxx respmag table 45 read respiration data magnitude 2 0x000000 r 0x1c xxxxxx respph table 46 read respiration data phase 2 0x000000 r 0x1d xxxxxx loff table 47 lead - off status 0x000000 r 0x1e xxxxxx dclea d- off table 48 dc lead - off 0x000000 r 0x1 f xxxxxx opstat table 49 operating state 0x000000 r/w 0x20 dddddd extendsw table 50 extended switch for respiration inputs 0x000000 r/w 0x21 dddddd calla table 51 user gain calibration la 0x000000 r/w 0x22 dddddd calll table 51 user gain calibration l l 0x000000 r/w 0x23 dddddd calra table 51 user gain calibration ra 0x000000 r/w 0x24 dddddd calv1 table 51 user gain calibration v1 0x000000 r/w 0x25 dddddd calv2 table 51 user gain calibration v2 0x000000 r 0x31 dddddd loamla table 52 lead - off amplitude for la 0x000000 r 0x32 dddddd loamll t able 52 lead - off amplitude for ll 0x000000 r 0x33 dddddd loamra table 52 lead - off amplitude for ra 0x000000 r 0x34 dddddd loamv1 table 52 lead - off amplitude for v1 0x0 00000 r 0x35 dddddd loamv2 table 52 lead - off amplitude for v2 0x000000 r 0x3a dddddd pace1data table 53 pace1 width and amplitude 2 0x000000 r 0x3b dddddd pace2data table 53 pace2 width and amplitude 2 0x000000 r 0x3c dddddd pace3data table 53 pace3 width and amplitude 2 0x000000 r 0x40 dddddd frames table 54 frame header 0x800000 r 0x41 xxxxxx crc table 55 fra me crc 0xffffff x other xxxxxx reserved 3 reserved xxxxxx 1 r/w = register both readable and writable; r = read only. 2 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . 3 reserved bits in any register are undefined. in some cases a physical (but unused) memory bit may be present in other cases not. do not issue commands to reserved registers/space. rea d operations of unassigned bits are undefined . rev. b | page 56 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 control registers details for each register address, the default setting is noted in a default column in addition to being noted in the f unction column by ( default ) ; this format applies throug hout the register map. table 27 . serial bit assignment b 31 [b 30:b 24] [b 23:b 0 ] r /w address bits data bits (msb first) table 28 . ecg control register ( ecgctl) address 0x01 , reset value = 0x 000000 r /w default bit name function r/w 0 23 laen ecg channel enable ; shuts down power to the channel ; the input becomes h i gh - z. r/w 0 22 llen 0 (default) = disables ecg channel. when disabled, the entire ecg channel is shut down and dissipating minimal power. r/w 0 21 raen r/w 0 20 v1en 1 = enables ecg channel. r/w 0 19 v2en r 0 [ 18:11 ] reserved reserved, set to 0 . r/w 0 10 chconfig setting this bit selects the differential analog front end ( afe ) input . see figure 58. 0 (default) = single - ended input (digital lead mode or electrode mode). 1 = differential input (analog lead mode). r/w 00 [ 9:8 ] gain [1:0] preamplifier and anti - aliasing filter overall gain . 00 (default) = gain 0 = 1.4. 01 = gain 1 = 2.1. 10 = gain 2 = 2.8. 11 = gain 3 = 4.2 (user gain calibration is required for this gain setting). r/w 0 7 vrefbuf vref buffer enable . 0 (default) = disabled. 1 = enabled (when using the intern al vref, vrefbuf must be enabled). r/w 0 6 clkext use external clock instead of crystal oscillator. the crystal oscillator is automatically disabled if configured as a slave in g ang mode , and the s lave device receives the clock from the m aster device. 0 (default) = xtal is clock source. 1 = clk_io is clock source. r/w 0 5 master in gang mod e, this bit selects the master ( sync_gang pin is configured as an output ). when in s ingle c hannel m ode ( gang = 0), this bit is ignored . adas1000 - 2 cannot be configured as a master device . 0 (default) = slave. 1 = master. r/w 0 4 gang enable gang mode. setting this bit causes clk _io and sync_gang to be activated. 0 ( default) = single channel mode. 1 = gang mode. r/w 0 3 hp sele cts the noise/power performance. this bit controls the adc sampling frequency. see the specifications section for further details. this bit also a ffects the respiration carrier frequency as discussed in the respiration carrier frequency section. 0 (default) = 1 msps, low power. 1 = 2 msps, high performance/low noise. r/w 0 2 cnven conver sion e nabl e . setting this bit enables the adc conversion and filters. 0 (default) = idle. 1 = conversion enable. r/w 0 1 pwren power e nable . clearing this bit powers down the device. all analog blocks are powered down and the external crystal is disabled . the register contents are retained during power down as long as dvdd is not removed. 0 (default) = power down. 1 = power enable. r/w 0 0 swrst software reset. setting this bit clears all registers to their reset value. this bit automatically clears itself. the software reset requires a nop command to complete the reset. 0 (default) = nop. 1 = reset. rev. b | page 57 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet table 29. lead - off control register (loffctl) address 0x02, reset value = 0x000000 r /w defau lt bit name function r/w 0 23 laph ac lead - off phase. r/w 0 22 llph 0 (default) = in phase. r/w 0 21 raph 1 = 180 out of phase. r/w 0 20 v 1ph r/w 0 19 v 2ph r/w 0 18 ceph r/w 0 17 laacloen individual electrode ac lead - off enable. ac lead - off en ables are the or of acsel and the individual ac lead - off channel enables. r/w 0 16 llacloen r/w 0 15 raacloen 0 (default) = ac lead - off disabled. r/w 0 14 v 1 acloen 1 = ac lead - off enabled. r/w 0 13 v 2 acloen r/w 0 12 ceacloen r 0 [ 11:9] reserved r eserved, set to 0. r/w 00 [ 8:7] accurrent set c urrent level for ac lead - off . 00 (default) = 12.5 na rms. 01 = 25 na rms. 10 = 50 na rms. 11 = 100 na rms. 00 [ 6:5] reserved reserved, set to 0 . r/w 000 [ 4:2] dccurrent set c urrent leve l for dc lead - off (active only for acsel = 0) . 000 (default) = 0 na. 001 = 10 na. 010 = 20 na. 011 = 30 na. 100 = 40 na. 101 = 50 na. 110 = 60 na. 111 = 70 na. r/w 0 1 acsel dc or ac (out -of - band) lead - off detectio n. acsel acts as a global ac lead - off enable for ra, ll, la, v 1, v 2 electrodes (ce ac lead - off is not enabled using acsel). ac lead - off enables are the or of acsel and the individual ac lead - off channel enables. if loffen = 0, this bit is dont c are. if loffen = 1, 0 (default) = dc lead - off detection enabled (individual ac lead - off can be enabled through bits[ 17:12]). 1 = dc lead - off detection disabled. ac lead - off detection enabled (all electrodes except ce electrode). when th e calibration dac is enabled, ac lead - off is disabled. r/w 0 0 loffen enable lead - off detection . 0 (default) = lead - off disabled. 1 = lead - off enabled. rev. b | page 58 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 30 . respiration control register (respctl) address 0x03, reset value = 0x000000 1 r /w default bit name function [23:17] reserved reserved, set to 0 . r/w 0 16 respaltfreq setting this bit to 1 makes the respiration waveform on the gpio3 pin periodic every cycle. use in conjunction with resfre q to select drive frequency . 0 (default) = periodic every n cycles (default). 1 = periodic every cycle. r/w 0 15 respextsync set this bit to 1 to drive the msb of the respiration dac out onto the gpio3 pin. this signal can be used to synchronize an external generator to the respiration carrier. it is a constant period only when respaltfreq = 1. 0 (default) = normal gpio3 function. 1 = msb of respdac driven onto gpio3 pin. r/w 0 14 respextamp for use with an external instrumentation am plifier with respiration circuit. bypasses the on - chip amplifier stage and input directly to the adc. see figure 71 . 0 (default) = disabled. 1 = enabled. r/w 0 13 respout selects e xt ernal respiration dr ive output. respdac _ra is automatically selected when res p cap = 1 0 (default) = respdac_ll and respdac_ra. 1 = respdac_la and respdac_ra. r/w 0 12 respcap selects source of respiration capacitors . 0 (default) = use internal capacitors. 1 = use external capacitors. r/w 0000 [ 11:8 ] respgain [3:0] respiration in amp gain (saturates at 10) . 0000 (default) = 1 gain. 0001 = 2 gain. 0010 = 3 gain. 1000 = 9 gain. 1001 = 10 gain. 11xx = 10 gain. r/w 0 7 respextsel selects between ext_resp _ la or ext_resp_ll paths . applies only if the external respiration is selected in respsel. ext_resp_ ra is automatically enabled. 0 (default) = ext_resp_ll. 1 = ext_resp_la. r/w 00 [ 6:5 ] respsel [1:0] set le ads for respiration measurement . 00 (default) = lead i. 01 = lead ii. 10 = lead iii. 11 = external respiration path. r/w 00 [ 4:3 ] respamp set the test tone amplitude for respiration drive signal . 00 (default) = amplitude/8. 01 = amplitude/4. 10 = amplitude/2. 11 = amplitude. r/w 00 [ 2:1 ] respfreq set frequency for respiration . respfreq respaltfreq = 0 respaltfreq = 1 (periodic) 00 (default) 56 khz 64 khz 01 54 khz 56.9 khz 10 52 khz 51.2 khz 11 50 khz 46.5 khz r/w 0 0 respen enable r espiration . 0 (default) = respiration disabled. 1 = respiration enabled. 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . rev. b | page 59 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 31 . pace detection control register (pacectl) address 0x04, reset value = 0x000f88 1 r /w default bit name function [23:12] reserved reserved, set to 0 r/w 1 11 pacefilt w pace width f ilter 0 = filter disabled 1 (default) = filter enabled r/w 1 10 pacetfilt 2 pace validation filter 2 0 = filter disabled 1 (def ault) = filter enabled r/w 1 9 pacetfilt 1 pace validation filter 1 0 = filter disabled 1 (default) = filter enabled r/w 11 [8:7] pace 3 sel [ 1:0] set lead for pace detection measurement r/w 00 [6:5] pace 2 sel [ 1:0] 00 = lead i r/w 01 [4:3] pace1 sel [ 1:0] 01 = lead ii 10 = lead iii 11 = lead avf r/w 0 2 pace 3 en enable pace detection algorithm r/w 0 1 pace 2en 0 (default) = pace detection disabled r/w 0 0 pace 1en 1 = pace detection enabled 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . rev. b | page 60 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 32 . common - mo de, reference , and shield drive control register (cmrefctl) address 0x05, reset value = 0xe00000 r /w default bit name function r/w 1 23 lacm common -m ode electrode select . r/w 1 22 llcm any combination of the five input electrodes can be used to create the common - mode signal, vcm. bits[23:19] are ignored when bit 2 is selected. common mode is the average of the selected electrodes. when a single electrode is selected, common mode is the signal level of that electrode alone. the common - mod e signal can be driven from the internal vcm_ref ( 1.3 v) when bits [ 23:19 ] = 0. r/w 1 21 racm r/w 0 20 v1cm r/w 0 19 v2cm 0 = does not contribute to the common mode. 1 = contributes to the common mode. 0 [18:15] reserved reserved, set to 0. r/w 0 14 larld rld summing junction . note that if the rld amplifier is disabled (using rldsel), these switches are not automatically forced open, and the user must disable them using b its [9: 14 ]. r/w 0 13 llrld r/w 0 12 rarld 0 (default) = does not contribute to rld input. r/w 0 11 v1 rld 1 = contributes to rld input. r/w 0 10 v2 rld r/w 0 9 cerld r/w 0 8 cerefen common electrode (ce) reference , see figure 58 . 0 (default) = common electrode disabled. 1 = common electrode enabled. r/w 0000 [7:4] r ld sel [3:0] 1 select electrode for reference drive . 0000 (default) = rld_out. 0001 = la. 0010 = ll. 0011 = ra. 0100 = v 1. 0101 = v 2. 0110 to 1111 = reserved. r/w 0 3 drvcm common - mode output. w hen set , the internally derived common - mode signal is driven out of the common - mode pin. this bit has no effect if an external common mode is selected. 0 (default) = common mode is not driven out. 1 = common mode is driven out of the external common - mode pin. r/w 0 2 extcm select the source of common mode (use when operating multiple devices together) . 0 (default) = internal common mode selected. 1 = external comm on mode selected (all the internal common - mode switches are off ). r/w 0 1 rldsel 1 enable right leg drive reference electrode . 0 (default) = disabled. 1 = enabled. r/w 0 0 shlden 1 enable shield d riv e. 0 (default) = shield drive disabled. 1 = shield drive enabled. 1 adas1000 and adas1000 -1 model s only, adas1000 -2 models do es not contain these features . rev. b | page 61 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 33 . gpio control register (gpioctl) address 0x06, reset value = 0x000000 r /w default bit name function 0 [23:19] reserved res erved, set to 0 r/w 0 18 spifw frame secon dary spi words with chip select 0 (default) = mcs asserted for entire frame 1 = mcs asserted for individual word r/w 0 17 reserved reserved, set to 0 r/w 0 16 spien secondary spi e nable ( adas1000 and adas1000 -1 only); spi interface providing ecg data at 128 khz data rate for external digital pace algorithm detection, uses gpio0, gpio1, gpio2 pins 0 (default) = disabled 1 = enabled; he individual control bits for gpio0, gpio1, gpio2 are ignored; gpio3 is not affected by spien r/w 00 [15:14] g3ctl [1:0] state of gpio3 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain r/w 0 13 g3out output v alue to be written to gpio3 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value r 0 12 g3in read o nly ; i nput v alue read from gpio3 when the pin is configured as an input 0 (default) = low value 1 = high value r/w 00 [11:10] g2ctl [1:0] state of gpio2 pin 00 ( default) = high impedance 01 = input 10 = output 11 = open drain r/w 0 9 g2out output v alue to be written to gpio2 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value r 0 8 g2in read o nly input value read from gpio2 when the pin is configured as an input 0 (default) = low value 1 = high value r/w 00 [7:6] g1ctl [1:0] state of gpio1 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain r/w 0 5 g1out output v alue to be written to gpio1 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value r 0 4 g1in read only; i nput value read from gpio1 when the pin is configured as an input 0 (default) = low value 1 = high value r/w 00 [3:2] g0ctl [1:0] state of the gpio0 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain r/w 0 1 g0out output v alue to be written to gpio0 when pin is configured as an output or open drain 0 (default) = low value 1 = high value r 0 0 g0in (read o nly) input value read from gpio0 when pin is configured as an input 0 (default) = low value 1 = high value rev. b | page 62 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 34 . pace amplitude thresh old register (paceampth) address 0x07, reset value = 0x242424 1 r /w default bit name function r/w 0010 0100 [23:16] pace 3 ampth pace amplitude threshold r/w 0010 0100 [ 15:8 ] pace 2 ampth threshold = n 2 vref/gain/2 16 r/w 0010 0100 [7:0] pace 1 ampth 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . table 35. test tone register (testtone) address 0x08, reset value = 0x000000 r /w default bit name function r/w 0 23 tonla tone s elect r/w 0 22 tonll 0 (default) = 1.3 v vcm_ref r/w 0 21 tonra 1 = 1 mv sine wave or square wave for tonint = 1, no connect for tonint = 0 r/w 0 20 tonv 1 r/w 0 19 tonv 2 r /w 0 [18:5] reserved reserved, set to 0 r/w 00 [4:3] ton type 00 (default) = 10 hz sine wave 01 = 150 hz sine wave 1 = 1 hz, 1 mv square wave r/w 0 2 tonint test tone internal or external 0 (default) = external test tone; test tone to be sent out through cal_dac_io and applied externally to enabled channels 1 = internal test tone; disconnects external switches for all ecg channe ls and connects the calibration dac test tone internally to all ecg channels; in gang mode, the cal_dac_io is connected, and the slave disables the calibration dac r/w 0 1 tonout test tone out enable 0 (default) = disconnects test tone from cal_dac_io during internal mode only 1 = connects cal_dac_io to test tone during internal mode r/w 0 0 tonen enables an internal test tone to drive entire signal chain, from preamp lifier to spi interface; t his tone comes from the c alibration dac and goes to the preamp lifier through the internal mux ; w hen tonen (calibration dac) is enabled, ac l ead - off is disabled 0 (default) = disable the test tone 1 = enable the 1 mv sine wave test tone (calibration mode has priority) rev. b | page 63 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 36 . calibration dac register (caldac) address 0x09, reset value = 0x002000 1 r /w default bit name function 0 [23:14] reserved reserved, set to 0 . r/w 1 13 calchpen calibration chop clock enable . the c alibration dac output (cal_dac_io) can be chopped to lower 1/f noise. chopping is performed at 256 khz. 0 = disabled. 1 (default) = enabled. r/w 0 12 calmodeen calibration mode enable . 0 (default) = disable calibration mode. 1 = enable calibration mode; connect cal d ac_io, begin data acquisition on ecg channels. r/w 0 11 calint calibration internal or external . 0 (default) = external calibration to be performed externally by looping cal_dac_io around into ecg channels. 1 = internal calibration; disconnects external switches for all ecg channels and connects calibration dac signal internally to all ecg channels. r/w 0 10 caldacen enable 10 - bit calibration dac for cal ibration mode or external use. 0 (default) = disable calibration dac. 1 = enable c alibration dac. if a master device and not in calibration mode, also connects the calibration dac signal out to the cal_dac_io pin for external use. if in slave mode, the calibration dac is disabled to allow master to drive the slave cal_dac_io pin. when t he calibration dac is enabled, ac lead - off is disabled. r/w 0000000000 [9:0] caldata[ 9:0] set the calibration dac value . 1 to ensure successful update of the calibration dac, the serial inte rface must issue four additional sclk cycles after writing the new calibration dac register word. rev. b | page 64 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 t able 37 . frame control register ( frmctl ) address 0x0a , reset value = 0x079000 r /w defau lt bit name function r/w 0 23 lead i/ladis include/exclude word from ecg data frame. if the electrode/lead is included in the data - word and the electrode falls off, the data - word is undefined. r/w 0 22 leadii/lldis r/w 0 21 leadiii/radis 0 (default) = included in frame. r/w 0 20 v1 dis 1 = exclude from frame. r/w 0 19 v2 dis r/w 1111 [18:15] reserved reserved , s et to 1111 . r/w 0 14 pacedis 1 pace detection . 0 (default) = included in frame. 1 = exclude from frame. r/w 0 13 respmdis 1 respiration m agnitude . 0 (default) = included in frame. 1 = exclude from frame. r/w 1 12 respphdis 1 respiration p hase . 0 = included in frame. 1 (def ault) = exclude from frame. r/w 0 11 loff dis lead - off s tatus . 0 (default) = included in frame. 1 = exclude from frame. r/w 0 10 gpiodis gpio w ord disable . 0 (default) = included in frame. 1 = exclude from frame. r/w 0 9 crcdis crc wo rd disable . 0 (default) = included in frame. 1 = exclude from frame. r /w 0 8 reserved reserved, set to 0 . r/w 0 7 adis automatically excludes pace dis [14], resp mdis [13] , loff dis [11] words i f their flags are not set in the header . 0 (defaul t) = fixed frame format. 1 = autodisable words (words per frame changes). r/w 0 6 rdyrpt ready r epeat . if this bit is set and the frame header indicates data is not ready, the frame header is continuously sent until data is ready. 0 (default) = always send entire frame. 1 = repeat frame header until ready. r/w 0 5 reserved reserved, set to 0 . r/w 0 4 datafmt sets the output data format , see figure 58 . 0 (default) = digital lead/vector format (available only in 2 khz and 16 khz data rates). 1 = electrode format. r/w 00 [3:2] skip[ 1:0] skip interval . t his field provides a way to decimate the data . 00 (default) = output every frame. 01 = output every other frame. 1 = output every 4 th frame. r/w 00 [1:0] frmrate[ 1:0] sets the output data rate . 00 (default) = 2 khz output data rate. 01 = 16 khz output data rate. 10 = 128 khz output data rate (datafmt must be set to 1). 11 = 31.25 hz. 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these featu res . rev. b | page 65 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet table 38 . filter control register ( filtctl ) address 0x0b , reset value = 0x000000 r /w default bit name function r/w 0 [ 23:6] reserved reserved, set to 0 r/w 0 5 mn 2k 2 khz notch bypass for spi m aster 0 (default) = notch filte r bypassed 1 = notch filter present r/w 0 4 n 2kbp 2 khz notch bypass 0 (default) = notch filter present 1 = notch filter bypassed r/w 00 [ 3:2] lpf[ 1:0] 00 (default) = 40 hz 01 = 150 hz 10 = 250 hz 11 = 450 hz r/w 00 [ 1:0] r eserved reserved, set to 0 table 39. ac lead - off upper threshold register ( loffuth ) address 0x0c , reset value = 0x00ffff r /w default bit name function 0 [ 23:20] reserved reserved, set to 0 r/w 0 [ 19:16] adcove r[ 3:0 ] adc over range threshold an adc out -of - range error is flagged if the adc output is greater than the overrange threshold; the overrange threshold is offset from the maximum value threshold = max_value C adcover 2 6 0000 = maximum value (dis abled) 0001 = max_value C 64 0010 = max_value C 128 1111 = max_value ? 960 r/w 0x ffff [ 15:0] loffuth[ 15:0] applies to ac l ead - off upper t hreshold only ; l ead - off is detected if the output is n 2 vref/gain/2 16 0 = 0 v table 40. ac lead - off lower threshold register ( lofflt h ) address 0x0d , reset value = 0x000000 r /w default bit name function 0 [ 23:20] reserved reserved, set to 0 r/w 0 [ 19:16] adcundr[ 3:0 ] adc under range threshold an adc out -of - range error is flagged if the adc output is less than th e underrange threshold threshold = min_value + adcundr 2 6 0000 = minimum value (disabled) 0001 = min_value + 64 0010 = min_value + 128 1111 = min_value + 960 r/w 0 [ 15:0] lofflth[ 15:0 ] applies to ac l ead - off lower t hreshold on ly ; l ead - off is detected if the output is n 2 vref/gain/2 16 0 = 0 v rev. b | page 66 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 41 . pace edge threshold register ( paceedg e th ) address 0x0e , reset value = 0x000000 1 r /w default bit name function r/w 0 [23:16] pace 3 edgth pace edge trigger threshold r/w 0 [15:8] pace 2 edgth 0 = paceampth/2 r/w 0 [7:0] pace 1 edgth 1 = vref/gain/2 16 n = n vref/gain/2 16 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . table 42 . pace level threshold register ( pacelvlth ) address 0x0f , reset va lue = 0x000000 1 r /w default bit name function r/w 0 [23:16] pace 3 lvlth[ 7:0] pace level threshold; t his is a signed value r/w 0 [ 15:8 ] pace 2 lvlth[ 7:0 ] ? 1 = 0xff = ?vref/gain/2 16 r/w 0 [7:0] pace 1 lvlth[ 7:0] 0 = 0x00 = 0 v +1 = 0x01 = +vref/gain/2 16 n = n vref/gain/2 16 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . table 43 . read electrode/lead data registers (electrode/lead ) address 0x11 to 0x 15 , reset value = 0x000000 1 r /w default bit name function [31:24] address [ 7:0] 0x11: la or lead i. 0x12 : ll or lead ii. 0x13 : ra or lead iii. 0x14 : v 1 or v 1. 0 x 15 : v 2 or v 2 . r 0 [23:0] ecg d ata channel data value. data left justif ied (msb) irrespective of data rate. the input stage can be configured into different modes (electrode, analog lead, or digital lead) as shown in table 11 . in electrode mode and analog lead mode, the digital result value is an unsigned integer. in digital lead/vector mode, the value is a signed twos complement integer format and has a 2 range compared to electrode format because it can swing from +vref to C vref; therefore, the lsb size is doubled. e lectrode mode and analog lead mode: minimum value ( 000 ) = 0 v maximum value ( 1111 .) = vref/gain lsb = (2 vref/gain)/(2n C 1) ecg (voltage) = ecg data (2 vref/gain)/(2n C 1) digital lead mode: minimum value ( 1000 ) = ?(vref/gain) maximum value ( 0111 .) = +vref/gain lsb = (4 vref/gain)/(2n C 1) ecg (voltage) = ecg data (4 vref/gain)/(2n C 1) where n = number of data bits: 16 for 128 khz data rate or 24 for 2 khz/ 16 khz data rate. 1 if using 128 khz data rate in frame mode, only the upper 16 bits are sent. if using the 128 khz data rate in regular read/write mode, all 32 bits are sent. rev. b | page 67 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 44 . read pace detection data /status register ( pacedata ) address 0x1a , reset value = 0x000000 1 , 2 , 3 r /w default bit name function r 0 23 pace 3 d etected pace 3 detected. this bit is set once a pace pulse is detect ed. this bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. r 000 [22:20] pace channel 3 w idth this bit is log 2 (w idth) ? 1 of the pace pulse. width = 2 n + 1 / 128 khz. r 0000 [19:16] pace channel 3 h eight this bit is the log 2 (height) of the pace pulse . height = 2 n vref/gain/2 16 . r 0 15 pace 2 d etected pace 2 detected. this bit is set once a pace pulse is det ected. this bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. r 000 [14:12] pace channel 2 w idth this bit is log 2 (w idth) ? 1 of the pace pulse. width = 2 n + 1 / 128 khz. r 0000 [11:8] pace channel 2 h eight this bit is the log 2 (height) of the pace pulse . height = 2 n vref/gain/2 16 . r 0 7 pace 1 d etected pace 1 detected. this bit is set once a pace pulse is detected. this bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. r 000 [6:4] pace channel 1 w idth this bit is log 2 (w idth) ? 1 of the pace pulse. width = 2 n + 1 / 128 khz. r 0000 [3:0] pace channel 1 h eight this bit is the log 2 (height) of the pace pulse . height = 2 n vref/gain/2 16 . 1 if using 128 khz data rat e in frame mode, this word is stretched over two 16 - bit words. if using the 128 khz data rate in regular read/write mode, all 32 bits are sent. 2 log data for width and height is provided here to ensure that it fits in one full 32 - bit data - word. as a resul t there may be some amount of error in the resulting value. for more accurate reading, read register 0x3a, register 0x3b, and register 0x3c (see table 53 ). 3 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . table 45 . read respiration data magnitude register ( resp mag ) address 0x1b , reset value = 0x000000 1, 2 r /w default bit name function r 0 [23:0] respiration m agnitude[ 23:0] magnitude of respiration signal. this is an unsigned value. 4 (vref/(1.6468 respiration gain))/(2 24 C 1 ). 1 if using 128 khz data rate in frame mode, this word is stretched over two 16 - bit words. if using the 128 khz data rate in regular read/write mode, all 32 bits are sent. 2 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . tabl e 46 . read respiration data phase register ( respph ) address 0x1c , reset value = 0x000000 1, 2 r /w default bit name function r 0 [23:0] respiration p hase[ 23:0] phase of respiration signal. can be interpreted as either signed or unsigned value. if unsigned, the range is from 0 to 2. if signed, the range is from C to + . 0x000000 = 0. 0x000001 = 2/2 24 . 0x400000 = / 2. 0x800000 = + = ? . 0xc 00000 = +3/ 2 = ? / 2. 0xffffff = +2(1 ? 2 ? 24 ) = ?2/2 24 . 1 this register is not part of framing data, but may be read by issuing a register read command of this address . 2 adas1000 model onl y, adas1000 -1 / adas1000 -2 models do not contain these features . rev. b | page 68 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 47. lead- off status register (loff ) address 0x1d , reset value = 0x000000 r /w default bit name function r 0 23 rld lead - off status electrode connection status. 22 la lead - off status if either dc or ac lead - off is enabled, these bits are the corresponding lead - off status. if both dc and ac lead - off are enabled, these bits reflect only the ac lead - off status. dc lead - off is available in the dclead- off register (see table 48). 21 ll lead - off status 20 ra lead - off status 19 v1 lead - off status the common electrodes have only dc lead - off detection. 18 v2 lead - off status an ac lead - off signal can be injected into the common electrode, but there is no adc input to measure its amplitude. if the common electrode is off, it affects the ac lead - off amplitude of the other electrodes. 13 celo these bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into th e spi buffer. 0 = electrode is connected. 1 = electrode is disconnected. rld lead - off is not detected in ac lead - off. r 0 [17:14] reserved reserved . r 0 12 laadcor adc out of range error . 11 lladcor these status bits indicate the result ing adc code is out of range. 10 raadcor these bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into the spi buffer. 9 v1 adcor 8 v2 adcor r 0 [7:0] reserved reserved . table 48 . dc lead- off register ( dclead -off ) address 0x1e , reset value = 0x0000 00 1 r /w default bit name function r 0 23 rl d input overrange the dc lead - off detection is comparator based and compares to a fixed level. individual electrode bits flag indicate if the dc lead - off comparator threshold level has been exceeded . 22 la input overrange 0 = electrode < overrange threshold, 2.4 v. 21 ll input overrange 1 = electrode > overrange threshold, 2.4 v. 20 ra input overrange 19 v1 input over range 18 v2 input overrange 13 ce input overrange r 0 [1 7:14] [6:3] reserved reserved . r 0 12 rl d input underrange the dc lead - off detection is comparator based and compares to a fixed level. individual electrode bits indicate if the dc lead - off comparator threshold level has been exceeded . 11 la input underrange 0 = electrode > underrange threshold, 0.2 v. 10 ll input underrange 1 = electrode < underrange threshold, 0.2 v. 9 ra input underrange 8 v1 input overrange 7 v2 input overrang e 2 ce input underrange r 0 [1:0] reserved 1 this register is not part of framing data, but can be read by issuing a register read command of this address . rev. b | page 69 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 49 . operating state register ( opstat ) address 0x1f , reset value = 0x000000 1 r /w default bit name function r 0 [23:4] reserved reserved . r 0 3 internal e rror internal d igital failure. this is set if a n error is detected in the digital core . r 0 2 configuration status this bit is set after a reset indicating that the configuration ha s not been read yet. once the configuration is set, this bit is ready . 0 = ready. 1 = busy. r 0 1 pll lock pll lock lost. this bit is set if the internal pll loses lock after it is enabled and locked. this bit is cleared once this register is read or the pwren bit (address 0x01[1]) is cleared . 0 = pll locked. 1 = pll lost lock. r 0 0 pll locked status this bit indicates the current state of the pll locked status. 0 = pll not locked. 1 = pll locked. 1 this register is not part of framing data, but can be read by issuing a register read command of this address . this register assists support efforts giving insight into potential areas of malfunction within a failing device. table 50 . extend ed switch for respiration inputs register ( extendsw ) addre ss 0x20 , reset value = 0x000000 r /w default bit name switch function r/w 0 23 ext_resp_ra to ecg1_la sw1a external respiration electrode input switch to channel electrode input (see figure 72). 1 22 ext_resp_ra to ecg2_ll sw1b 21 ext _ resp_ra to ecg3 _ ra sw1c 0 = switch open. 20 ext _ resp_ra to ecg4 _v1 sw1d 1 = switch closed. 19 ext _ resp_ra to ecg5 _v2 sw1e 18 ext _ resp_ll to ecg1 _la sw2a 17 ext _ resp_ll to ecg2 _ll sw2b 16 ext _r esp_ll to ecg3 _ra sw2c 15 ext _ resp_ll to ecg4 _v1 sw2d 14 ext _ resp_ll to ecg5 _v2 sw2e 13 ext _ resp_la to ecg1 _la sw3a 12 ext _ resp_la to ecg2 _ ll sw3b 11 ext _ resp_la to ecg3 _ra sw3c 10 ext _ resp_la to ecg4 _v1 sw3d 9 ext _ resp_la to ec g5 _v2 sw3e r/w 0 8 aux_v1 v1 and v2 electrodes can be used for measurement purposes other than ecg. r/w 0 7 aux_v2 to achieve this, they must be disconnected from the patient vcm voltage provided from the internal common - mode buffer and, instead, con nected to the internal vcm_ref level of 1.3 v. setting the aux_vx bits high connects the negative input of the v1 and v2 channel amplifier to internal vcm_ref level. this allows the user to make alternative measurements on v1 and v2 relative to the vcm_ref level. note that the v1 and v2 measurements are now being made outside of the right leg drive loop, therefore there is increa sed noise on the measurement as a result. r/w 0 [6 :0] reserved reserved , set to 0 . 1 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these ext_resp_xx pins. rev. b | page 70 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 51 . user gain calibration registers ( calxx ) address 0x21 to address 0x 25 , reset value = 0x000000 r /w default bit name function [31:24] address [7:0] 0x21: calibration la . 0x22 : calibration ll. 0x23 : calibration ra. 0x24 : calibration v 1. 0x25 : calibration v 2. r/w 0 23 usrcal user can choose between default calibration values or user calibration values for gain 0, gain 1, gain 2. note that for gain 3 , there is no factory calibration. 0 = default calibrat ion values (factory calibration). 1 = user calibration values. r/w 0 [22:12] reserved reserved , set to 0 r/w 0 [ 11:0 ] calvalue gain calibration value. result = data (1 + gain 2 ? 17 ). the value read from this register is the current gain calibration value. if the usrcal bit is set to 0 , this register returns the default value for the current gain setting. 0x7ff (+2047) = 1.00000011111111111b. 0x001 (+1) = 1.00000000000000001b. 0x000 (0) = 1.00000000000000000b. 0xfff (?1) = 0.11111111111111111b. 0x800 (?2048) = 0.11111100000000000b. table 52 . read ac lead - off amplitude registers (loam xx ) address 0x31 to address 0x35 , reset value = 0x000000 1 r /w default bit name function [31:24] address [7:0] 0x31: la ac lead - off a mplitude . 0x32 : ll ac lead - off amplitude. 0x33 : ra ac lead - off amplitude. 0x34 : v 1 ac lead - off amplitude. 0x35: v2 ac lead - off amplitude. r/w 0 [23:16] reserved reserved . r 0 [15:0] loffam measured amplitude . when ac lead - off is selected, the data is the average of the rectified 2 khz band - pass filter with an update rate of 8 hz and cutoff frequency at 2 hz. the output is the amplitude of the 2 khz signal scaled by 2 / approximately = 0.6 (average of rectified sine wave). to convert to rms, scale the output by /( 22 ). lead - off (unsigned). minimum 0x0000 = 0 v. lsb 0x0001= vref/gain/2 16 . maximum 0xff ff = vref/gain. rms = [/(2 2)] [(code vref)/(gain 2 16 )] peak -to - peak = [(code vref)/(gain 2 16 )] 1 this register is not part of framing data, but can be read by issuing a regi ster read command of this address . rev. b | page 71 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet table 53 . pace width and amplitude registers ( pace x data ) address 0x3a to address 0x 3c , reset value = 0x000000 1, 2 r /w default bit name function [31:24] address [ 7:0] 0x3 a: pace 1 data 0x3 b: pace 2 data 0x3 c: pace 3 data r 0 [23:8] pace height measured pace height in signed two s complement value 0 = 0 1 = vref/gain/2 16 n = 2 n vref/gain/2 16 r 0 [7:0] pace width measured pace width in 128 khz samples n: (n + 1 )/ 128 khz = width 12 : ( 12 + 1 )/ 128 khz = 101.56 s (minimum when pace width filter enabled) 255: ( 255 + 1)/ 128 khz = 2.0 ms disabling t he pace width filter allows the pace measurement system to return values of n < 12 , that is, pulses narrower than 101.56 s. 1 these registers are not part of framing data but can be read by issuing a register read command of these addresses. 2 adas1000 model only, adas1000 -1 / adas1000 -2 models do not contain these features . rev. b | page 72 of 80
data sheet adas1000/adas1000 - 1/adas1000 -2 table 54 . frame header ( frames ) address 0x40 , reset value = 0x800000 1 r /w default bit name function r 1 31 marker header marker, set to 1 for the header . r 0 30 ready b it ready bit indicates if ecg frame data is calculated and ready for reading. 0 = ready, data frame follows. 1 = busy. r 0 [29:28] ov erflow [1:0] overflow bits indicate that since the last frame read, a number of frames have been missed. this field saturates at the maximum count. the data in the frame including this header word is valid but old if the overflow bits are > 0. when usi ng skip mode (frmctl register ( 0x0 a), bits[ 3:2 ]), the overflow bit acts as a flag, where a nonzero value indicates an overflow. 00 = 0 missed. 01 = 1 frame missed. 10 = 2 frames missed. 11 = 3 or more frames missed. r 0 27 fault intern al device error detected. 0 = normal operation. 1 = error condition. r 0 26 pace 3 d etected pace 3 i ndicates pacing artifact was qualified at most recent point. 0 = no pacing artifact. 1 = pacing artifact present. r 0 25 pace 2 d etected pace 2 indicates pacing artifact was qualified at most recent point . 0 = no pacing artifact. 1 = pacing artifact present. r 0 24 pace 1 d etected pace 1 indicates pacing artifact was qualified at most recent point . 0 = no pacing artifact. 1 = pacing artifact present. r 0 23 respiration 0 = no new respiration data . 1 = respiration data updated. r 0 22 lead - off detected if both dc and ac lead - off are enabled, this bit is the or of all the ac lead - off detect flags. if only ac or d c lead - off is enabled, this bit reflects the or of all dc and ac lead - off flags. 0 = all leads connected. 1 = one or more lead - off detected. r 0 21 dc l ead - off detected 0 = all leads connected . 1 = one or more lead - off detected. r 0 20 adc out of range 0 = adc within range . 1 = adc out of range. 0 [19:0] reserved reserved 1 if using 128 khz data rate in frame mode, only the upper 16 bits are sent. if using the 128 khz data rate in regular read/write mode, all 32 bits are sent. table 55. frame crc register ( crc ) address 0x41 , reset value = 0xffffff 1 r /w bit name function r [23:0] crc cyclic red undancy check 1 the crc register is a 32- bit word for 2 khz and 16 khz data rate and a 16 - bit word for 128 khz rate. see table 24 for more details. rev. b | page 73 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet examples of interfac ing to the adas1000 the following examples shows register commands required to configure the adas1000 device into particular mode s of operation and to start framing ecg data. example 1: i nitialize the adas1000 for ecg capture and start strea ming data 1. write 1 configures the cmrefctl register for cm = wct = (la + ll + ra)/3 ; rld is enabled onto the rl d_out electrode. the shield amplifier is enabled. 2. write 2 configures the frmctl register to output nine words per frame/packet. the frame/packet of words consist of the h eader, five ecg words, pace, respiration magnitude, and lead - off . the f rame is configured to always send , irrespective of ready status . t he adas1000 i s in analog lead format mode with a data rate of 2 khz. 3. write 3 addresses the ecgctl register, enabling all channels into a gain of 1.4, low noise mode , and differen - tial input, which configures the device for a nalog l ead mode . this register also configur es the device as a m aster , using the external crystal as the input source to the xtalx pins . the adas1000 is also put into conversion mode in this write. 4. write 4 issues the read command to start putting the converted data out on the sdo pin. 5. continue to issue sclk cycles to read the converted data at the configured packet data rate (2 khz). the sdi input must be held low when reading back the conversion data because any commands issued to the interface during read of frame/packet are understood to be a change of configu - ration data and stop the adc conversions to allow the interface to process the new command. example 2: enable respiration and stream conversion data 1. write 1 con figures the respctl register with a 56 khz respiration drive signal, gain = 1, driving out through the respiration capacitors and measuring on lead i. 2. write 2 issues the read command to start putting the converted data out on the sdo pin. 3. continue to is sue sclk cycles to read the converted data at the configured packet data rate. 4. note that this example assumes that the frmctl register has already been configured such that the respiration magnitude is available in the data frame, as arr anged in write 2 o f example 1. example 3: dc lead - off and stream conversion data 1. write 1 configures the loffctl register with a dc lead - off enabled for a lead - off current of 50 na. 2. write 2 issues the read command to start putting the converted data out on the sdo pin. 3. co ntinue to issue sclk cycles to read the converted data at the configured packet data rate. 4. note that this example assumes that the frmct l register has already been configured such that the dc lead - off word is available in the data frame, as arranged in w rite 2 of example 1 . table 56. example 1: i nitialize the adas1000 for ecg capture and start streaming data write command register addressed read/write b it register address data 32- bit write command write 1 cmrefctl 1 000 0101 1110 0000 0000 0000 0000 1011 0x85e0000b write 2 frmctl 1 000 1010 0000 0111 1001 0110 0000 0000 0x8a079600 write 3 ecgctl 1 000 0001 1111 1000 0000 0100 1010 1110 0x81f804ae wri te 4 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 table 57 . example 2: enable respiration and stream conversion data write command register addressed read/write bit register address data 32- bit write command write 1 respctl 1 000 0011 0000 0000 0010 0000 1001 1001 0x83002099 write 2 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 table 58 . example 3 : enable dc lead - off and stream conversion data write command register addressed read/write bit register address data 32- bit write command write 1 loffctl 1 000 0010 0000 0000 0000 0000 0001 0101 0x82000015 write 2 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 rev. b | page 74 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 example 4: configure 150 hz test tone sine w ave on each ecg channel and stream conversion data 1. write 1 configures the cmrefctl register to vcm_ref = 1.3 v (no electrodes contribute to vcm) . rld is enabled to rl d_out , and the s hield amplifier enabled. 2. write 2 addresses the testtone register to enable the 150 h z sine wave onto all electrode channels . 3. write 3 addresses the filtctl register to change the internal low - pass filter to 250 hz to ensure that the 150 hz sine wave can pass through. 4. write 4 configures the frmctl register to output nine words per frame/pac ket. the frame/packet of words consist s of the h eader and five ecg words, pace, respiration magnitude , and l ead- off . the f rame is configured to always send , irrespective of ready status . the adas1000 is in e lectrode format mode with a data rate of 2 khz. electrode format is required to see the test tone signal correctly on each electrode channel. 5. write 5 addresses the ecgctl register , enabling all channels int o a gain of 1.4, low noise mode. i t configures the device as a m aster and driven from the xtal input source. the adas1000 is also put into conversion mode in this write. 6. write 6 issues the read com mand to start putting the converted data out on the sdo pin. 7. continue to issue sclk cycles to read the converted data at the configured packet data rate. example 5: enable pace detection and stream conversion data 1. write 1 configures the pacectl register with all three p ace detection instances enabled, pace1 en detecting on lead ii, pace2 en detecting on lead i, and pace 3 en detecting on lead avf. the pace width filter and validation filters are also enabled. 2. write 2 issues the read command to start putting the converted data out on the sdo pin. 3. continue to issue sclk cycles to read the converted data at the configured packet data rate. when a valid p ace is detected, the detection flags are confirmed in the h eader word and the pacedata register contain s infor mation on the width and height of the measured pulse from each measured lead. 4. note that the paceampth register default setting is 0x242424, setting the amplitude of each of the p ace instances to 1.98 mv/ g ain. 5. note that this example assumes that the frmc tl register has already been configured such that the pacedata word is available in the data frame, as arranged in write 2 of example 1 . table 59 . example 4 : configure 150 hz test tone sine wave on each ecg channel and stream conve rsion data write command register addressed read / write bit register address data 32- bit write command write 1 cmrefctl 1 000 0101 0000 0000 0000 0000 0000 1011 0x8500000b write 2 testtone 1 000 1000 1111 1000 0000 0000 0000 1101 0x88f8000d write 3 filtc tl 1 000 1011 0000 0000 0000 0000 0000 1000 0x8b000008 write 4 frmctl 1 000 1010 0000 0111 1001 0110 0001 0000 0x8a079610 write 5 ecgctl 1 000 0001 1111 1000 0000 0000 1010 1110 0x81f800ae write 6 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000 000 table 60 . example 5 : enable pace detection and stream conversion data write command register addressed read/write bit register address data 32- bit write command write 1 pacectl 1 000 0100 0000 0000 0000 1111 1000 1111 0x8400 0f8f write 2 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 rev. b | page 75 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet example 6: writing to master and slave devices and streaming conversion data slave configuration 1. write 1 configures the frmctl register to output seven words per frame/packet. t he frame/packet of words consist of the h eader, five ecg words , and l ead- off . the f rame is configured to always send , irrespective of ready status . the s lave adas1000 - 2 is in e lectrode mode format with a data rate of 2 khz. 2. write 2 configures the cmrefctl register to receive an external common mode from the master. 3. write 3 addresses the ecgctl register, enabling all channels into a gain of 1.4, low noise mode . it configures th e device as a slave , i n gang mode and driven from the clk _ in input source (derived from m aster adas1000 ). the adas1000 - 2 s lave is also put into conversion mode in this write, but waits for the sync_gang signal from the m aster device before it starts converting. master configuration 1. write 4 configures the frmctl register to output nine words per frame/packet (note that this differs from the number of words in a frame available from the s lave device) . the frame/packet of words consist s of the h eader, five ecg words, pace, respiration m agnitude, and l ead - off . in this example, t he f rame is configure d to always send irrespective of ready status . t he m aster , adas1000 , is in v ector mode format with a data rate of 2 khz. similar to the slave device, the master could be configu red for electrode mode; the host controller would then be required to make the lead calculations. 2. write 5 configures the cmrefctl register for cm = wct = (la + ll + ra)/3 ; rld is enabled onto rl d_out electrode. the shield amplifier is enabled. the cm = w ct signal is driven out of the m aster device (cm_out) into the s lave device (cm_in). 3. write 6 addresses the ecgctl register, enabling all channels i nto a gain of 1.4, low noise mode. it configures the device as a master i n gang mode and driven from the x tal input source. the adas1000 m aster is set to differential input, which places it in analog lead mode . this ecgctl register write put s the master into conversion mode , where t he device sends an edge on the sync_gang pin to the s lave device to trigger the simultaneous conversions of both devices. 4. write 7 issues the read command to start putting the converted and decimated data out on the sdo pin. 5. continue to issue sclk cycles to read the converted data at the configured packet data rate. table 61 . example 6: writing to master and slave devices and streaming conversion data device write command register addressed r/w register address data 32- bit write command slave write 1 frmctl 1 000 1010 0000 0111 1111 0110 0001 0000 0x8a07f610 write 2 cmrefctl 1 000 0101 0000 0000 0000 0000 0000 0100 0x8500000 4 write 3 ecgctl 1 000 0001 1111 1000 0000 0000 1101 1110 0x81f800de master write 4 frmct l 1 000 1010 0000 0111 1001 0110 0000 0000 0x8a079600 write 5 cmrefctl 1 000 0101 1110 0000 0000 0000 0000 1011 0x85e0000b write 6 ecgctl 1 000 0001 1111 1000 0000 0100 1011 1110 0x81f80 4 be write 7 frames 0 100 0000 0000 0000 0000 0000 0000 0000 0x4 0000000 rev. b | page 76 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 software flowchart figure 84 shows a suggested sequence of steps to be taken to interface to multiple adas1000 / adas1000 - 1 / adas1000 - 2 devices. figure 84 . suggested software flowchart for interfacing to multiple adas1000 / adas1000 - 1 / adas1000 - 2 devices is crc correct? drdy low? power up adas1000 devices adas1000 goes into power-down mode 09660-038 wait for por routine to complete, 1.5ms initialize slave devices initialize master device enabling conversion issue read frame com mand (write to 0x40) discard frame data issue sclk cycles (sdi = 0) to clock frame data out at programmed data rate activity on sdi? return to ecg capture? power-down? yes yes yes yes yes no no no no no issue read frame command (write to 0x40) ecg capture complete power-down adas1000 ecgctl = 0x0 adas1000 stops converting, sdi word used to reconfigure device rev. b | page 77 of 80
adas1000/adas1000 - 1/adas1000 - 2 data sheet p ower supply, groundi ng , and decoupling strategy the adas1000 / adas1000 - 1 / adas1000 - 2 must have ample supply decoupling of 0. 0 1 f on each supply pin located as close to the device pin as possible, ideally right up against the device. in addition , there must be one 4.7 f capacitor for each of the power domain s, avdd and iovdd, again located as close to the device as possible . iovd d is best split from avdd due to its noisy nature. s imilarly, the adcvdd and dvdd power domains each require one 2.2 f capacitor with esr in the range of 0.5 to 2 . the ideal location for each 2.2 f capacitor is dependent on package type. for the lqf p package and dvdd decoupling, the 2.2 f capac itor is best placed between pin 30 and pin 31, while for adcvdd , place the 2.2 f capacitor between pin 55 and pin 56. similarly for the lfcsp package, the dvdd 2.2 f capacitor is ideal between pin 43 and pin 44, and between pin 22 and pin 23 for adcvdd . a 0.01 f capacitor is recommended for high frequency decoupling at each pin. th e 0.01 f capacitor s must have low effective series resistance (esr) and effective series inductance (esl), such as the common ce ramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. avoid d igital lines running under the device because these couple noise onto the device. allow t he analog ground plane to run under the device to avoid noise coupling. the power supply lines must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. shield f ast switching digital signals with digi tal ground to avoid radiating noise to other parts of the board and never run them near the reference inputs. it is essential to minimize noise on vref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board must run at right angles to each other. this reduces the effects of feedthrough throughout the board. as is the case for all thin packages, take care to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. dur ing layout of board, ensure that bypass capacitors are placed as close to the relevant pin as possible, with short, wide traces ideally on the topside. avdd while the adas1000 / adas1000 - 1 / adas1000 - 2 are designed to operate f rom a wide supply rail, 3 .15 v to 5.5 v, the performance is similar over the full range, but overall power increase s with increasing voltage. adcvdd and dvdd suppl ies the avdd supply rail powers the analog blocks in addition to the internal 1.8 v regul ators for the adc and the digital core. if using the internal regulators , connect the vreg_en pin to avdd and then use the adc vdd and dvdd pins for decoupling purposes. the dvdd regulator can be used to drive other externa l digital circuitry as required; however the adcvdd pin is purely provided for bypassing purposes and does not have available current for other components. where overall power consumption must be minimized, using external 1.8 v supply rails for both adcvdd and dvdd would provide a more efficient solution. the adcvdd and dvdd inputs have been designed to be driven externally and the internal regulators can be disabled by tying vreg_en pin directly to ground . unused p ins/paths in applications where not all ecg paths or functions might be used, the preferred method of biasing the different functions is as follows: ? u nused ecg paths power up disabled. f or low power operation, keep them disabled throughout operation. ideally, connect these pins to rl d_out if not being used. ? unused external re spiration inputs can be tied to ground if not in use. ? if unused , the s hield driver can be disabled and output left to float. ? cm _out , cal_dac _io , drdy , gpiox , clk _io, sync_gang can be left open . layout r ecommendations to maximize cmrr pe rformance, pay careful attention to the ecg path layout for each channel. all channels must be identical to minimize difference in capacitance across the paths. place a ll decoupling as close to the adas1000 / adas1000 - 1 / adas1 000 - 2 device s as possible, with an emphasis on ensuring that the vref decoupling be prioritized, with vref decoupling on the same side as the adas1000 / adas1000 - 1 / adas1000 - 2 device s, where possible. rev. b | page 78 of 80
data sheet adas1000/adas1000 - 1/adas1000 - 2 outline dimensions fi gure 85 . 56- lead , lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 56 - 7) dimensions shown in millimeters figure 86 . 64 - lead low profile quad flat package [ lqfp ] (st - 64- 2) di mensions shown in millimeters 06-20-2012- a 8.75 bsc sq 1 14 42 29 15 28 56 43 0.75 0.65 0.55 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 6.50 ref 6.05 5.95 sq 5.85 9.10 9.00 sq 8.90 0.50 bsc 0.20 ref 12 max 0.05 max 0.01 nom 0.70 max 0.65 nom sea ting plane t o p view pin 1 indic a t or 0.90 0.85 0.80 bot t om view 0.275 0.150 * exposed pad * for proper connection of the exposed pad, refer to the pin configurations and function descriptions section of this data sheet. compliant t o jedec s t andards ms-026-bcd 051706- a t o p view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 rev. b | page 79 of 80
adas1000/adas1000 - 1/adas1000 -2 data sheet ordering guide model 1 description temperature range package description package option adas1000 bstz 5 ecg channels, pace algorithm, respiration circuit ?40 c to + 85c 64- lead lqfp st-64-2 adas1000 bstz -rl 5 ecg channels, pace algorithm, respiration circuit ?40 c to + 85c 64- lead lqfp st-64-2 adas1000 bcpz 5 ecg channels, pace algorithm, respiration circuit ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 adas1000 bcpz -rl 5 ecg channels, pace algorithm, respiration circuit ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 adas1000-1 bcpz 5 ecg channels ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 adas 1000-1 bcpz -rl 5 ecg channels ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 adas1000-2 bstz companion for gang mode ?40 c to + 85c 64- lead lqfp st-64-2 adas 1000-2 bstz -rl companion for gang mode ?40 c to + 85c 64- lead lqfp st-64-2 adas 1000-2 bcpz companion for gang mode ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 adas 1000-2 bcpz -rl companion for gang mode ?40 c to + 85c 56- lead lfcsp_vq cp-56-7 eval - adas 1000sdz adas 1000 evaluation board evaluation kit 2 eval -sdp-cb1z system demonstration board (sdp), used as a controller board for data transfer via usb interface to pc controller board 3 1 z = rohs compliant part. 2 this evaluation kit consists of adas1000bstz 2 for up to 12 - lead configuration. because the adas1000 contains all features, it is the evaluation vehicle for all adas1000 variants. 3 this board allows a p c to control and communicate with all analog devices evaluation boards ending in the sd designator. ? 2012 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09660 -0- 6/14(b) rev. b | page 80 of 80

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